View HT66F019_8965577.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

a/d flash mcu with eeprom HT66F019 revision: v1.00 date: de?e??e? 01? ?01? de?e??e? 01? ?01?
rev. 1.00 ? de?e??e? 01? ?01? rev. 1.00 3 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom table of contents eates cpu featu?es ......................................................................................................................... ? pe?iphe?al featu?es ................................................................................................................. ? gene?al des??iption ......................................................................................... 8 blo?k diag?a? .................................................................................................. 8 pin assign?ent ................................................................................................ 9 pin des??iption ................................................................................................ 9 a?solute maxi?u? ratings ........................................................................... 11 d.c. cha?a?te?isti?s ........................................................................................ 11 ope? ating voltage cha?a?te?isti?s .......................................................................................... 11 stand?y cu??ent cha?a?te?isti?s ........................................................................................... 1? ope?ating cu??ent cha?a?te?isti?s ......................................................................................... 13 a.c. cha?a?te?isti?s ....................................................................................... 14 high speed inte?nal os?illato? C hirc C f?equen? y a??u?a?y ............................................. 14 low speed inte?nal os?illato? cha?a?te?isti?s C lirc .......................................................... 14 ope?ating f?equen?y cha?a?te?isti? cu?ves ......................................................................... 15 syste? sta? t up ti?e cha?a?te?isti?s .................................................................................. 15 input/output cha?a?te?isti?s ........................................................................ 16 me?o?y cha?a?te?isti?s ................................................................................ 16 a/d conve?te? ele?t?i?al cha?a?te?isti?s ..................................................... 1? refe?en?e voltage cha?a?te?isti?s ............................................................... 1? lvd/lvr ele?t?i?al cha?a?te?isti?s .............................................................. 1? co?pa?ato? cha?a?te?isti?s ......................................................................... 18 powe?-on reset cha?a?te?isti?s ................................................................... 18 syste? a??hite?tu?e ...................................................................................... 19 clo?king and pipelining ......................................................................................................... 19 p?og?a? counte? ................................................................................................................... ?0 sta?k ..................................................................................................................................... ?0 a?ith?eti? and logi? unit C alu ........................................................................................... ?1 flash p?og?a? me?o?y ................................................................................. ?? st?u?tu?e ................................................................................................................................ ?? spe? ial ve?to?s ..................................................................................................................... ?? look-up ta ?le ........................................................................................................................ ?? ta ?le p?og?a? exa?ple ........................................................................................................ ?3 in ci??uit p?og?a??ing C icp ............................................................................................... ?4 on-chip de?ug suppo?t C ocds ......................................................................................... ?5 data me?o?y .................................................................................................. ?6 st?u?tu?e ................................................................................................................................ ?6 gene?al pu?pose data me?o?y ............................................................................................ ?6
rev. 1.00 ? de?e??e? 01? ?01? rev. 1.00 3 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom spe?ial pu?pose data me?o?y ............................................................................................. ?6 special function register description ........................................................ 28 indi?e? t add?essing registe? C iar0? iar1 ........................................................................... ?8 me?o?y pointe?s C mp0? mp1 .............................................................................................. ?8 bank pointe? C bp ................................................................................................................. ?9 a??u?ulato? C acc ............................................................................................................... ?9 p?og?a? counte? low registe? C pcl .................................................................................. ?9 look-up ta ? le registe? s C tblp ? tbhp ? tblh ..................................................................... ?9 status registe? C status .................................................................................................... 30 eeprom data memory .................................................................................. 32 eeprom data me?o?y st?u?tu?e ........................................................................................ 3? eeprom registe?s .............................................................................................................. 3? reading data f?o? the eeprom ......................................................................................... 34 w ?iting data to the eeprom ................................................................................................ 34 w ?ite p?ote?tion ..................................................................................................................... 34 eeprom inte??upt ................................................................................................................ 34 p?og?a??ing conside?ations ................................................................................................ 35 oscillators ...................................................................................................... 36 os?illato? ove?view ............................................................................................................... 36 system clock confgurations ................................................................................................ 36 exte?nal c?ystal/ce?a?i? os?illato? C hxt ........................................................................... 3? inte?nal rc os?illato? C hirc ............................................................................................... 38 exte?nal 3?.?68khz c?ystal os?illato? C lxt ........................................................................ 38 inte?nal 3?khz os?illato? C lirc ........................................................................................... 39 supple?enta?y os?illato?s .................................................................................................... 39 operating modes and system clocks ......................................................... 40 syste? clo?ks ...................................................................................................................... 40 syste? ope?ation modes ...................................................................................................... 41 cont?ol registe?s .................................................................................................................. 4? fast wake-up ....................................................................................................................... 43 ope?ating mode swit?hing .................................................................................................... 44 stand?y cu??ent conside?ations ........................................................................................... 48 wake-up ................................................................................................................................ 48 p?og?a??ing conside?ations ................................................................................................ 49 watchdog timer ............................................................................................. 50 wat ? hdog ti?e? clo?k sou??e .............................................................................................. 50 wat ? hdog ti?e? cont?ol registe? ......................................................................................... 50 wat ? hdog ti?e? ope?ation ................................................................................................... 51 reset and initialisation .................................................................................. 52 reset fun?tions .................................................................................................................... 5? reset initial conditions ........................................................................................................ 54 input/output ports ......................................................................................... 57 pull-high resisto?s ................................................................................................................ 5? po? t a wake-up ..................................................................................................................... 58
rev. 1.00 4 de?e??e? 01? ?01? rev. 1.00 5 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom i/o po?t cont?ol registe?s ..................................................................................................... 58 pin-?e?apping fun?tion ........................................................................................................ 58 i/o pin st?u?tu?es .................................................................................................................. 59 p?og?a??ing conside?ations ............................................................................................... 60 timer modules C tm ...................................................................................... 61 int?odu?tion ........................................................................................................................... 61 tm ope?ation ........................................................................................................................ 61 tm clo?k sou??e ................................................................................................................... 61 tm inte??upts ......................................................................................................................... 6? tm exte?nal pins .................................................................................................................. 6? tm input/output pin cont?ol registe? ................................................................................... 6? p?og?a??ing conside?ations ................................................................................................ 64 compact type tm C ctm .............................................................................. 65 co?pa? t type tm ope?ation ................................................................................................ 65 co?pa? t type tm registe? des??iption ................................................................................ 65 co?pa? t type tm ope? ating modes .................................................................................... 69 standard type tm C stm .............................................................................. 75 standa? d type tm ope?ation ................................................................................................ ?5 standa? d type tm registe? des??iption ............................................................................... ?5 standa? d type tm ope? ation modes .................................................................................... ?9 periodic type tm C ptm ................................................................................ 89 pe?iodi? type tm ope?ation .................................................................................................. 89 pe?iodi? type tm registe? des??iption ................................................................................. 89 pe?iodi? type tm ope? ation modes ...................................................................................... 93 analog to digital converter ....................................................................... 102 a/d conve?te? ove?view ..................................................................................................... 10? a/d conve?te? registe? des??iption .................................................................................... 103 a/d conve?te? ope?ation ..................................................................................................... 106 a/d conve?te? refe?en? e voltage ....................................................................................... 10? a/d conve?te? input signals ................................................................................................ 10? conve? sion rate and ti?ing diag?a? ................................................................................ 108 su??a? y of a/d conve?sion steps .................................................................................... 108 p?og?a??ing conside?ations .............................................................................................. 109 a/d conve?sion fun?tion .................................................................................................... 109 a/d conve?sion p?og?a??ing exa?ples ............................................................................. 110 comparator ................................................................................................... 112 co?pa?ato? ope?ation ......................................................................................................... 11 ? co?pa?ato? inte??upt ............................................................................................................ 11 ? p?og?a??ing conside?ations ............................................................................................... 11 ? serial interface module C sim ...................................................................... 114 spi inte?fa?e ........................................................................................................................ 114 i ? c inte?fa?e ........................................................................................................................ 1?1
rev. 1.00 4 de?e??e? 01? ?01? rev. 1.00 5 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom uart interface ............................................................................................. 131 uart exte ?nal pins ............................................................................................................ 13? uart data t ?ansfe? s?he?e .............................................................................................. 13? uart status and cont ?ol registe?s .................................................................................... 13? baud rate gene?ato? .......................................................................................................... 138 uart setup and cont ?ol ..................................................................................................... 139 uart t ?ans?itte? ................................................................................................................ 140 uart re ?eive? ................................................................................................................... 141 managing re?eive? e??o?s .................................................................................................. 143 uart inte ??upt st?u?tu?e ..................................................................................................... 144 uart powe ? down and wake-up ....................................................................................... 145 interrupts ...................................................................................................... 146 inte??upt registe?s ............................................................................................................... 146 inte??upt ope?ation .............................................................................................................. 150 exte?nal inte??upts ............................................................................................................... 15? co?pa?ato? inte??upt ........................................................................................................... 15? multi-fun?tion inte??upts ....................................................................................................... 15? a/d conve?te? inte??upt ....................................................................................................... 153 ti ?e base inte??upts ........................................................................................................... 153 se?ial inte?fa?e module inte??upt ......................................................................................... 154 uart t ?ansfe? inte??upt ...................................................................................................... 154 eeprom w ?ite inte??upt ..................................................................................................... 154 lvd inte ??upt ....................................................................................................................... 155 tm inte??upts ...................................................................................................................... 155 inte?? upt wake-up fun?tion ................................................................................................. 155 p?og?a??ing conside?ations .............................................................................................. 156 low voltage detector C lvd ....................................................................... 157 lvd registe ? ....................................................................................................................... 15? lvd ope ?ation ..................................................................................................................... 158 confguration options ................................................................................. 159 application circuits ..................................................................................... 159 instruction set .............................................................................................. 160 int?odu?tion ......................................................................................................................... 160 inst?u? tion ti?ing ................................................................................................................ 160 moving and t ?ansfe??ing data ............................................................................................. 160 a?ith?eti? ope?ations .......................................................................................................... 160 logi?al and rotate ope?ation ............................................................................................. 161 b?an?hes and cont? ol t ?ansfe? ........................................................................................... 161 bit ope?ations ..................................................................................................................... 161 ta ?le read ope?ations ....................................................................................................... 161 othe? ope?ations ................................................................................................................. 161
rev. 1.00 6 de?e??e? 01? ?01? rev. 1.00 ? de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom instruction set summary ............................................................................ 162 ta ?le conventions ............................................................................................................... 16? instruction defnition ................................................................................... 164 package information ................................................................................... 173 ? 0-pin nsop (150?il) outline di?ensions ......................................................................... 1?4
rev. 1.00 6 de?e??e? 01? ?01? rev. 1.00 ? de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom features cpu features ? operating voltage f sys =8mhz: 2.2v~5.5v f sys =12mhz: 2.7v~5.5v f sys =16mhz: 3.3v~5.5v ? up to 0.25 s instruction cycle with 16mhz system clock at v dd =5v ? power down and wake-up functions to reduce power consumption ? oscillator types: external high speed crystal C hxt internal high speed rc C hirc external low speed 32.768khz crystal C lxt internal low speed 32khz rc C lirc ? multi-mode operation: fast, slow, idle and sleep ? fully integrated internal oscillators require no external components ? all instructions executed in one or two instruction cycles ? table read instructions ? 63 powerful instructions ? 8-level subroutine nesting ? bit manipulation instruction peripheral features ? flash program memory: 8k16 ? ram data memory: 256 8 ? true eeprom memory: 64 8 ? watchdog timer function ? up to 18 bidirectional i/o lines with led direct driving capability ? dual external interrupt lines shared with i/o pin ? multiple timer modules for time measurement, capture input, compare match output or pwm output or single pulse output function ? comparator function ? dual time-base functions for generation of fxed time interrupt signals ? up to 8 external channels 12-bit resolution a/d converter ? serial interface module includes spi and i 2 c interfaces ? fully-duplex universal asynchronous receiver and transmitter interface C uart ? low voltage reset function ? low voltage detect function ? package type: 20-pin nsop
rev. 1.00 8 de?e??e? 01? ?01? rev. 1.00 9 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom general description the device is a flash memory type 8-bit high performance risc architecture microcontroller. offering users the convenience of flash memory multi-programming features, the device also includes a wide range of functions and features. other memory includes an area of ram data memory as well as an area of true eeprom memory for storage of non-volatile data such as serial numbers, calibration data etc. analog features include a multi-channel 12-bit a/d converter and a comparator functions. multiple and extremely flexible timer modules provide timing, pulse generation and pwm generation functions. communication with the outside world is catered for by including fully integrated spi, i 2 c, and uart interface functions, popular interfaces which provide designers with a means of easy communication with external peripheral hardware. protective features such as an internal watchdog timer, low voltage reset and low voltage detector coupled with excellent noise immunity and esd protection ensure that reliable operation is maintained in hostile electrical environments. a full choice of external and internal low and high oscillator functions are provided including fully integrated system oscillators which require no external components for their implementation. the ability to operate and switch dynamically between a range of operating modes using different clock sources gives users the ability to optimise microcontroller operation and minimise power consumption. the inclusion of fexible i/o programming features, time-base functions along with many other features ensure that the devices will fnd excellent use in applications such as electronic metering, environmental monitoring, handheld instruments, household appliances, electronically controlled tools, motor driving in addition to many others. block diagram inte??upt cont?olle? sfr mux sysclk lvd/lvr sta?k 8-level ram ?56 8 rom 8k 16 eeprom 64 8 wat?hdog ti?e? po?t a d?ive? hirc 8/1?/16mhz lirc 3?khz pin-re?apping fun?tion int0~ int1 pin-sha?e with po?t b ti?e bases co?pa?ato? pin-sha?e with po?t a & b hxt lxt pin-sha?e with po?t b & c xt1 xt? osc1 osc? pa0~pa? pb0~pb6 pc0~pc? po?t b d?ive? po?t c d?ive? ht8 mcu co?e clo?k syste? ti?e?s digital pe?iphe?als uart i/o an0~an? pin-sha?e with po?t a & b vref pin-sha?e with po?t a + cmp _ c+ c- cx : pin-sha?e node v dd mux v bgref analog digital conve?te? 1?-?it adc analog pe?iphe?als v dd vdd v ss vss : sim in?luding spi and i ? c sim
rev. 1.00 8 de?e??e? 01? ?01? rev. 1.00 9 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom pin assignment HT66F019/ht66v019 20 nsop-a vss pc0/osc1 pc1/osc? pc? pa0/stp/icpda/ocdsda pa1/sdo pa?/icpck/ocdsck pa3/sdi/sda/cx pb6/sck/scl/c+ pb5/scs/c- vdd pb0/int0/an0/xt1 pb1/int1/an1/xt? pb?/stck/an? pa4/ptck/an3 pa5/an4/vref pa6/tx/ctck/an5 pa?/rx/ptp/an6 pb3/[tx]/ctp/an? pb4/[rx]/clo ?0 19 18 1? 16 15 14 13 1? 11 1 ? 3 4 5 6 ? 8 9 10 notes: 1. bracketed pin names indicate non-default pinout remapping locations. the detailed information can be referenced to the relevant chapter. 2. if the pin-shared pin functions have multiple outputs simultaneously, its pin names at the right side of the "/" sign can be used for higher priority. 3. the ocdsda and ocdsck pins are supplied for the ocds dedicated pins and as such only available for the ht66v019 device which is the ocds ev chip for the HT66F019 device. pin description with the exception of the power pins and some relevant transformer control pins, all pins on the device can be referenced by their port name, e.g. pa0, pa1 etc., which refer to the digital i/o function of the pins. however these port pins are also shared with other function such as the timer module pins etc. the function of each pin is listed in the following table, however the details behind how each pin is confgured is contained in other sections of the datasheet. pin name function opt i/t o/t description pa0/stp/icpda/ ocdsda pa0 papu pawu st cmos gene?al pu?pose i/o. registe? ena?led pull-high and wake-up stp tmpc st cmos stm input/output icpda st cmos in-?i??uit p?og?a??ing add?ess/data pin ocdsda st cmos ocds data/add?ess pin? fo? ev ?hip only pa1 /sdo pa1 papu pawu st cmos gene?al pu?pose i/o. registe? ena?led pull-high and wake-up sdo simc0 cmos spi se?ial data output pa ?/icpck/ ocdsck pa ? papu pawu st cmos gene?al pu?pose i/o. registe? ena?led pull-high and wake-up icpck st in-?i??uit p?og?a??ing ?lo?k pin ocdsck st ocds ?lo?k pin? fo? ev ?hip only pa3 /sdi/sda /cx pa3 papu pawu st cmos gene?al pu?pose i/o. registe? ena?led pull-high and wake-up sdi simc0 st spi se?ial data input sda simc0 st nmos i ? c data line cx cpc cmos co?pa?ato? output
rev. 1.00 10 de?e??e? 01? ?01? rev. 1.00 11 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom pin name function opt i/t o/t description pa4/ptck/an3 pa4 papu pawu st cmos gene?al pu?pose i/o. registe? ena?led pull-high and wake-up ptck ptmc0 st ptm ?lo?k input an3 acerl an a/d conve?te? exte?nal input 3 pa5/an4/vref pa5 papu pawu st cmos gene?al pu?pose i/o. registe? ena?led pull-high and wake-up an4 acerl an a/d conve?te? exte?nal input 4 vref tmpc an a/d conve?te? ?efe?en?e voltage input pin pa6/tx/ctck/ an5 pa6 papu pawu st cmos gene?al pu?pose i/o. registe? ena?led pull-high and wake-up. tx ifs cmos uart tx se ?ial data output ctck ctmc0 st ctm ?lo?k input an5 acerl an a/d conve?te? exte?nal input 5 pa ?/rx/ptp/ an6 pa ? papu pawu st cmos gene?al pu?pose i/o. registe? ena?led pull-high and wake-up rx ifs st uart rx se ?ial data input ptp tmpc st cmos ptm input/output an6 acerl an a/d conve?te? exte?nal input 6 pb0/int0/an0/ xt1 pb0 pbpu st cmos gene?al pu?pose i/o. registe? ena?led pull-high int0 intc0 integ st exte?nal inte??upt 0 an0 acerl an a/d conve?te? exte?nal input 0 xt1 co lxt low f?equen?y ??ystal pin pb1/int1/an1/ xt? pb1 pbpu st cmos gene?al pu?pose i/o. registe? ena?led pull-high int1 intc? integ st exte?nal inte??upt 1 an1 acerl an a/d conve?te? exte?nal input 1 xt? co lxt low f?equen?y ??ystal pin pb?/stck/an? pb? pbpu st cmos gene?al pu?pose i/o. registe? ena?led pull-high stck stmc0 st stm ?lo?k input an? acerl an a/d conve?te? exte?nal input ? pb3/[tx]/ctp/ an? pb3 pbpu st cmos gene?al pu?pose i/o. registe? ena?led pull-high tx ifs cmos uart tx se ?ial data output ctp tmpc cmos ctm output an? acerl an a/d conve?te? exte?nal input ? pb4/[rx]/clo pb4 pbpu st cmos gene?al pu?pose i/o. registe? ena?led pull-high rx ifs st uart rx se ?ial data input clo tmpc st cmos syste? ?lo?k output pb5/ scs /c- pb5 pbpu st cmos gene?al pu?pose i/o. registe? ena?led pull-high scs simc0 st cmos spi slave sele?t c- cpc an co?pa?ato? input pb6/sck/scl/ c+ pb6 pbpu st cmos gene?al pu?pose i/o. registe? ena?led pull-high sck simc0 st cmos spi se?ial ?lo?k scl simc0 st nmos i ? c ?lo?k line c+ cpc an co?pa?ato? input pc0/osc1 pc0 pcpu st cmos gene?al pu?pose i/o. registe? ena?led pull-high osc1 co hxt high f?equen?y ??ystal pin
rev. 1.00 10 de?e??e? 01? ?01? rev. 1.00 11 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom pin name function opt i/t o/t description pc1/osc? pc1 pcpu st cmos gene?al pu?pose i/o. registe? ena?led pull-high osc? co hxt high f?equen?y ??ystal pin pc? pc? pcpu st cmos gene?al pu?pose i/o. registe? ena?led pull-high vdd vdd pwr powe? supply vss vss pwr g?ound legend: i/t: input type; o/t: output type; opt: optional by confguration option (co) or register option; pwr: power; co: confguration option; st: schmitt trigger input; an: analog signal; cmos: cmos output; hxt: high frequency crystal oscillator; lxt: low frequency crystal oscillator. absolute maximum ratings supply voltage ................................................................................................. v ss -0.3v to v ss +6.0v input voltage ................................................................................................... v ss - 0.3v to v dd +0.3v storage temperature .................................................................................................... -50 ? c to 125?c operating temperature .................................................................................................. -40 ? c to 85 ? c i ol total ..................................................................................................................................... 80ma i oh total .................................................................................................................................... - 80ma total power dissipation ......................................................................................................... 500mw note: these are stress ratings only. stresses exceeding the range specified under "absolute maximum ratings" may cause substantial damage to the device. functional operation of the devices at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. d.c. characteristics for data in the following tables, note that factors such as oscillator type, operating voltage, operating frequency, pin load conditions, temperature and program instruction type, etc., can all exert an infuence on the measured values. operating voltage characteristics 7d & symbol parameter test conditions min. typ. max. unit v dd ope? ating voltage C hxt f sys = 8mhz ?.? 5.5 v f sys = 1?mhz ?.? 5.5 f sys = 16mhz 3.3 5.5 ope? ating voltage C hirc f sys = 8mhz ?.? 5.5 v f sys = 1?mhz ?.? 5.5 f sys = 16mhz 3.3 5.5 ope?ating voltage C lxt f sys = f lxt = 3?.?68khz ?.? 5.5 v ope?ating voltage C lirc f sys = f lirc = 3?khz ?.? 5.5 v
rev. 1.00 1? de?e??e? 01? ?01? rev. 1.00 13 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom standby current characteristics ta = 25?c symbol standby mode test conditions min. typ. max. max. unit v dd conditions 85 c i stb sleep mode ?.?v wdt off 0.1 0.6 0.? a 3v 0.? 0.8 1.0 5v 0.5 1.0 1.? ?.?v wdt on 1.? ?.4 ?.9 a 3v 1.5 3.0 3.6 5v ?.5 5.0 6.0 idle0 mode ?.?v f sub on ?.4 4.0 4.8 a 3v 3.0 5.0 6.0 5v 5.0 10 1? idle1 mode C hirc ?.?v f sub on? f sys = 8mhz C 0.3 0.6 0.8 ?a 3v 0.5 1.0 1.8 5v 1.0 ?.0 ?.? ?.?v f sub on? f sys = 1?mhz 0.4 0.8 1.0 ?a 3v 0.6 1.? 1.4 5v 1.? ?.4 ?.6 3.3v f sub on? f sys = 16mhz 1.5 3.0 3.? ?a 5v ?.0 4.0 4.? idle1 mode C hxt ?.?v f sub on? f sys = 8mhz 0.3 0.6 0.8 ?a 3v 0.5 1.0 1.? 5v 1.0 ?.0 ?.? ?.?v f sub on? f sys = 1?mhz 0.4 0.8 1.0 ?a 3v 0.6 1.? 1.4 5v 1.? ?.4 ?.6 3.3v f sub on? f sys = 16mhz 1.5 3.0 3.? ?a 5v ?.0 4.0 4.? 1rwhv :khqxvlqjwkhfkdudfwhulvwlfwdeohgdwdwkhiroorzlqjqrwhvvkrxogehwdnhqlqwrfrqvlghudwlrq qgljlwdolqsxwvduhvhwxslqdqrqrdwlqjfrqglwlrq oophdvxuhphqwvduhwdnhqxqghufrqglwlrqvriqrordgdqgzlwkdooshulskhudovlqdq riivwdwh ?khuhduhqr'&fxuuhqwsdwkv oo 6wdqge &xuuhqw ydoxhv duh wdnhq diwhu d +/? lqvwuxfwlrq h[hfxwlrq wkxv vwrsslqj doo lqvwuxfwlrq h[hfxwlrq
rev. 1.00 1? de?e??e? 01? ?01? rev. 1.00 13 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom operating current characteristics ta = ?5 ?c symbol operating mode test conditions min. typ. max. unit v dd conditions i dd slow mode lirc ?.?v f sys = 3?khz 8.0 16 a 3v 10 ?0 5v 30 50 slow mode lxt ?.?v f sys = 3?.?68khz 8.0 16 a 3v 10 ?0 5v 30 50 fast mode hirc ?.?v f sys = 8mhz 0.8 1.? ?a 3v 1.0 1.5 5v ?.0 3.0 ?.?v f sys = 1?mhz 1.? ?.? ?a 3v 1.5 ?.?5 5v 3.0 4.5 3.3v f sys = 16mhz 3.? 4.8 ?a 5v 4.5 ?.0 fast mode hxt ?.?v f sys = 8mhz 0.8 1.? ?a 3v 1.0 1.5 5v ?.0 3.0 ?.?v f sys = 1?mhz 1.? ?.? ?a 3v 1.5 ?.?5 5v 3.0 4.5 3.3v f sys = 16mhz 3.? 4.8 ?a 5v 4.5 ?.0 1rwhv :khqxvlqjwkhfkdudfwhulvwlfwdeohgdwdwkhiroorzlqjqrwhvvkrxogehwdnhqlqwrfrqvlghudwlrq qgljlwdolqsxwvduhvhwxslqdqrqrdwlqjfrqglwlrq oophdvxuhphqwvduhwdnhqxqghufrqglwlrqvriqrordgdqgzlwkdooshulskhudovlqdq riivwdwh ?khuhduhqr'&fxuuhqwsdwkv oo?shudwlqj&xuuhqwydoxhvduhphdvxuhgxvlqjdfrqwlqxrxv1?3 lqvwuxfwlrqsurjudporrs
rev. 1.00 14 de?e??e? 01? ?01? rev. 1.00 15 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom a.c. characteristics for data in the following tables, note that factors such as oscillator type, operating voltage, operating frequency and temperature etc., can all exert an infuence on the measured values. high speed internal oscillator C hirc C frequency accuracy during the program writing operation the writer will trim the hirc oscillator at a user selected hirc frequency and user selected voltage of 3v or 5v . 8/12/16mhz symbol parameter test conditions min. typ. max. unit v dd temp. f hirc 8mhz w ?ite? t ?i??ed hirc f?equen?y 3v/5v ?5c -1% 8 +1% mhz -40c ~ 85c -?% 8 +?% ?.?v~5.5v ?5c -?.5% 8 +?.5% -40c ~ 85c -3% 8 +3% 1?mhz w ?ite? t ?i??ed hirc f?equen?y 3v/5v ?5c -1% 1? +1% mhz -40c ~ 85c -?% 1? +?% ?.?v~5.5v ?5c -?.5% 1? +?.5% -40c ~ 85c -3% 1? +3% 16mhz w ?ite? t ?i??ed hirc f?equen?y 5v ?5c -1% 16 +1% mhz -40c ~ 85c -?% 16 +?% 3.3v~5.5v ?5c -?.5% 16 +?.5% -40c ~ 85c -3% 16 +3% notes: 1. the 3v/5v values for v dd are provided as these are the two selectable fxed voltages at which the hirc frequency is trimmed by the writer. 2. the row below the 3v/5v trim voltage row is provided to show the values for the full v dd range operating voltage. it is recommended that the trim voltage is fxed at 3v for application voltage ranges from 2.2v to 3.6v and fxed at 5v for application voltage ranges from 3.3v to 5.5v. 3. the minimum and maximum tolerance values provided in the table are only for the frequency at which the writer trims the hirc oscillator. after trimming at this chosen specifc frequency any change in hirc oscillator frequency using the oscillator register control bits by the application program will give a frequency tolerance to within 20%. low speed internal oscillator characteristics C lirc symbol parameter test conditions min. typ. max. unit v dd temp. f lirc lirc f?equen?y 5v & -10% 3? +10% khz ?.?v~5.5v &a& -50% 3? +60%
rev. 1.00 14 de?e??e? 01? ?01? rev. 1.00 15 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom operating frequency characteristic curves system operating frequency operating voltage 1?mhz ?.?v ?.?v 5.5v ~ ~ 8mhz 16mhz 3.3v ~ ~ system start up time characteristics ta = 25?c symbol parameter test conditions min. typ. max. unit t sst syste? sta? t-up ti?e wake-up f ?o? ?ondition whe?e f sys is off f sys = f lxt 1?8 t lxt f sys = f hxt ~ f hxt /64 1?8 t hxt f sys = f hirc ~ f hirc /64 16 t hirc f sys = f lirc ? t lirc syste? sta? t-up ti?e wake-up f ?o? ?ondition whe?e f sys is on f sys = f h ~ f h /64? f h = f hxt o? f hirc ? t h f sys = f lxt o? f lirc ? t sub syste? sta? t-up ti?e wdt overfow hardware cold reset 0 t h t rstd syste? reset delay ti?e reset sou??e f?o? powe?-on ?eset o? lvr ha?dwa?e ?eset ?5 50 100 ?s syste? reset delay ti?e lvrc/wdtc softwa ?e ?eset syste? reset delay ti?e reset source from wdt overfow 8.3 16.? 33.3 ?s t sreset mini?u? softwa?e ?eset width to ?eset 45 90 1?0 s otes 1. for the system start-up time values, whether f sys u ii ghshg s h pgh sh dg h hi sys hp ooduhdoduhsuyghgh6hpshudghh h ph h po sys h duh h yhuh i h uuhsg iuhh ydohdsuyghghiuhhdohuhdpsoh i sys i sys h h 6hp 6shhg 6 ph hiihyho h ph dh iu h ho dydhg oodu du s
rev. 1.00 16 de?e??e? 01? ?01? rev. 1.00 1? de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom input/output characteristics ta = 25?c symbol parameter test conditions min. typ. max. unit v dd conditions v il input low voltage fo ? i/o po?ts o? input pins 5v 0 1.5 v 0 0.?v dd v ih input high voltage fo ? i/o po?ts o? input pins 5v 3.5 5.0 v 0.8v dd v dd i ol sink cu??ent fo? i/o pins 3v v ol = 0.1v dd 16 3? ?a 5v 3? 64 i oh po?t sou??e cu??ent fo? i/o pins 3v v oh = 0.9v dd -5.5 -11 ?a 5v -11 -?? r ph pull-high resistan?e fo? i/o po?ts (note) 3v ?0 60 100 k 5v 10 30 50 t tck tm tck input pin mini ?u? pulse width 0.3 s t int inte??upt input pin mini?u? pulse width 10 s 1rwh ?kh 5 ph hudo soo uhdh ydoh doodhg h ug dg hdo h s s d soo uhu dg h phdu h s uuh d h shhg sso yodh ohyho yghyodhphduhguuhsuyghh ph ydoh memory characteristics ta = -40?c~85?c symbol parameter test conditions min. typ. max. unit v dd conditions v rw v dd fo? read / w ?ite v dd?in v dd?ax v flash program / data eeprom memory t dew e?ase / w ?ite cy? le ti?e C flash p?og?a? me?o?y ? 3 ?s w ?ite cy? le ti?e C data eeprom me?o?y 4 6 ?s i ddpgm p?og?a??ing / e?ase cu??ent on v dd 5.0 ?a e p cell endu?an?e 100k e/w t retd rom data retention ti ?e ta = 25?c 40 yea ? ram data memory v dr ram data retention voltage devi? e in sleep mode 1.0 v
rev. 1.00 16 de?e??e? 01? ?01? rev. 1.00 1? de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom a/d converter electrical characteristics ta = -40?c~85?c, unless otherwise specify symbol parameter test conditions min. typ. max. unit v dd conditions v dd ope? ating voltage ?.? 5.5 v v adi input voltage 0 v ref v v ref refe?en? e voltage ? v dd v dnl diffe ?ential non-linea?ity 3v v ref = v dd ? t adck = 0.5 s -3 + 3 lsb 5v 3v v ref = v dd ? t adck = 10s 5v inl integ?al non-linea?ity 3v v ref = v dd ? t adck = 0.5 s -4 + 4 lsb 5v 3v v ref = v dd ? t adck =10 s 5v i adc additional cu??ent consu?ption fo? a/d conve?te? ena?le 3v no load? t adck = 0.5 s 1 ? ?a 5v 1.5 3 t adck clo?k pe?iod 0.5 10 s t adc conve? sion ti?e (a/d sa? ple and hold ti?e) 16 t adck t on?st a/d conve?te? on-to-sta? t ti?e 4 s reference voltage characteristics ta = ?5c symbol parameter test conditions min. typ. max. unit v dd conditions v bg bandgap refe?en? e voltage -3% 1.?5 +3% v t bgs v bg tu ? n on sta? le ti?e no load ?00 s 1rwh ?kh 9 bg yodhdohgdh yhuhusdo lvd/lvr electrical characteristics ta = ?5c symbol parameter test conditions min. typ. max. unit v dd conditions v lvr low voltage reset voltage lvr ena ?le? voltage sele?t ?.1v -5% ?.1 +5% v lvr ena ?le? voltage sele?t ?.55v ?.55 lvr ena ?le? voltage sele?t 3.15v 3.15 lvr ena ?le? voltage sele?t 3.8v 3.8 v lvd low voltage dete ?to? voltage lvd ena ?le? voltage sele?t ?.0v -5% ?.0 +5% v lvd ena ?le? voltage sele?t ?.?v ?.? lvd ena ?le? voltage sele?t ?.4v ?.4 lvd ena ?le? voltage sele?t ?.?v ?.? lvd ena ?le? voltage sele?t 3.0v 3.0 lvd ena ?le? voltage sele?t 3.3v 3.3 lvd ena ?le? voltage sele?t 3.6v 3.6 lvd ena ?le? voltage sele?t 4.0v 4.0
rev. 1.00 18 de?e??e? 01? ?01? rev. 1.00 19 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom symbol parameter test conditions min. typ. max. unit v dd conditions i op ope?ating ?u??ent 5v lvd ena ?le? lvr ena?le? vbgen = 0 60 90 a 5v lvd ena ?le? lvr ena?le? vbgen = 1 180 ?00 t lvds lvdo sta ?le ti?e fo? lvr ena?le? vbgen = 0? lvd off on 15 s fo? lvr disa?le? vbgen = 0? lvd off on 150 t lvr mini?u? low voltage width to reset 1?0 ?40 480 s t lvd mini?u? low voltage width to inte??upt 60 1?0 ?40 s comparator characteristics ta = ?5 c symbol parameter test conditions min. typ. max. unit v dd conditions i cmp additional cu??ent fo? co?pa?ato? ena?le 3v 3? 56 a 5v 130 ?00 v os input offset voltage 3v -10 10 ?v 5v -10 10 v cm co?? on mode voltage range v ss v dd -1.4 v a ol open loop gain 3v 60 80 db 5v 60 80 v hys hyste?esis 3v chyen = 0 0 0 5 ?v 5v 0 0 5 3v chyen = 1 40 60 80 ?v 5v 40 60 80 t rp response ti ?e 3v with 100?v ove?d?ive 3?0 560 ns 5v 3?0 560 1rwh oophdvxuhphqwlvxqghu&lqsxwyrowdjh 9 dd dguhpdd power-on reset characteristics ta = 25?c symbol parameter test conditions min. typ. max. unit v dd conditions v por v dd sta? t voltage to ensu?e powe?-on reset 100 ?v rr por v dd rising rate to ensu?e powe?-on reset 0.035 v/?s t por mini?u? ti?e fo? v dd stays at v por to ensu?e powe?-on reset 1 ?s v dd t por rr por v por ti?e
rev. 1.00 18 de?e??e? 01? ?01? rev. 1.00 19 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom system architecture a key factor in the high-performance features of the holtek range of microcontrollers is attributed to their internal system architecture. the range of the device take advantage of the usual features found within risc microcontrollers providing increased speed of operation and enhanced performance. the pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. an 8-bit wide alu is used in practically all instruction set operations, which carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. the internal data path is simplifed by moving data through the accumulator and the alu. certain internal registers are implemented in the data memory and can be directly or indirectly addressed. the simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional i/o and a/d control system with maximum reliability and flexibility. this makes the device suitable for low-cost, high-volume production for controller applications. clocking and pipelining the main system clock, derived from either a hxt, lxt, hirc or lirc oscillator is subdivided into four internally generated non-overlapping clocks, t1~t4. the program counter is incremented at the beginning of the t1 clock during which time a new instruction is fetched. the remaining t2~t4 clocks carry out the decoding and execution functions. in this way, one t1~t4 clock cycle forms one instruction cycle. although the fetching and execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. the exception to this are instructions where the contents of the program counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. for instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. an extra cycle is required as the program takes one cycle to frst obtain the actual jump or call address and then another cycle to actually execute the branch. the requirement for this extra cycle should be taken into account by programmers in timing sensitive applications. fet?h inst. (pc+?) exe?ute inst. (pc+1) pc pc+1 pc+? fet?h inst. (pc+1) exe?ute inst. (pc) exe?ute inst. (pc-1) fet?h inst. (pc) f sys (syste? clo?k) phase clo?k t1 phase clo?k t? phase clo?k t3 phase clo?k t4 p?og?a? counte? pipelining system clocking and pipelining
rev. 1.00 ?0 de?e??e? 01? ?01? rev. 1.00 ?1 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom exe?ute inst. 1 fet?h inst. ? 1 mov a? [1?h] ? call delay 3 cpl [1?h] 4: 5: 6 delay: nop fet?h inst. 1 exe?ute inst. ? fet?h inst. 3 flush pipeline fet?h inst. 6 exe?ute inst. 6 fet?h inst. ? instruction fetching program counter during program execution, the program counter is used to keep track of the address of the next instruction to be executed. it is automatically incremented by one each time an instruction is executed except for instructions, such as "jmp" or "call" that demand a jump to a non- consecutive program memory address. only the lower 8 bits, known as the program counter low register, are directly addressable by the application program. when executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the program counter. for conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. program counter high byte low byte (pcl) pc1?~pc8 pcl?~pcl0 program counter the lower byte of the program counter, known as the program counter low register or pcl, is available for program control and is a readable and writeable register. by transferring data directly into this register, a short program jump can be executed directly; however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory that is 256 locations. when such program jumps are executed it should also be noted that a dummy cycle will be inserted. manipulating the pcl register may cause program branching, so an extra cycle is needed to pre-fetch. stack this is a special part of the memory which is used to save the contents of the program counter only. the stack is organized into 8 levels and neither part of the data nor part of the program space, and is neither readable nor writeable. the activated level is indexed by the stack pointer, and is neither readable nor writeable. at a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return instruction, ret or reti, the program counter is restored to its previous value from the stack. after a device reset, the stack pointer will point to the top of the stack. if the stack is full and an enabled interrupt takes place, the interrupt request fag will be recorded but the acknowledge signal will be inhibited. when the stack pointer is decremented, by ret or reti, the interrupt will be serviced. this feature prevents stack overfow allowing the programmer to use the structure more easily. however, when the stack is full, a call subroutine instruction can still be executed which will result in a stack overfow. precautions should be taken to avoid such cases which might cause unpredictable program branching. if the stack is overfow, the frst program counter save in the stack will be lost.
rev. 1.00 ?0 de?e??e? 01? ?01? rev. 1.00 ?1 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom sta?k pointe? sta?k level ? sta?k level 1 sta?k level 3 : : : sta?k level 8 p?og?a? me?o?y p?og?a? counte? botto? of sta?k top of sta?k arithmetic and logic unit C alu the arithmetic-logic unit or alu is a critical area of the microcontroller that carries out arithmetic and logic operations of the instruction set. connected to the main microcontroller data bus, the alu receives related instruction codes and performs the required arithmetic or logical operations after which the result will be placed in the specifed register. as these alu calculation or operations may result in carry, borrow or other status changes, the status register will be correspondingly updated to refect these changes. the alu supports the following functions: ? arithmetic operations: add, addm, adc, adcm, sub, subm, sbc, sbcm, daa ? logic operations: and, or, xor, andm, orm, xorm, cpl, cpla ? rotation rra, rr, rrca, rrc, rla, rl, rlca, rlc ? increment and decrement inca, inc, deca, dec ? branch decision, jmp, sz, sza, snz, siz, sdz, siza, sdza, call, ret, reti
rev. 1.00 ?? de?e??e? 01? ?01? rev. 1.00 ?3 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom flash program memory the program memory is the location where the user code or program is stored. for the device the program memory is flash type, which means it can be programmed and re-programmed a large number of times, allowing the user the convenience of code modifcation on the same device. by using the appropriate programming tools, the flash devices offer users the fexibility to conveniently debug and develop their applications while also offering a means of field programming and updating. structure the program memory has a capacity of 8k16 bits. the program memory is addressed by the program counter and also contains data, table information and interrupt entries. table data, which can be setup in any location within the program memory, is addressed by a separate table pointer register. 0000h 0004h 1fffh initialisation ve?to? inte??upt ve?to? 16 ?its 00?ch program memory structure special vectors within the program memory, certain locations are reserved for the reset and interrupts. the location 000h is reserved for use by the device reset for program initialisation. after a device reset is initiated, the program will jump to this location and begin execution. look-up table any location within the program memory can be defned as a look-up table where programmers can store fxed data. to use the look-up table, the table pointer must frst be setup by placing the address of the look up data to be retrieved in the table pointer register, tblp and tbhp. these registers defne the total address of the look-up table. after setting up the table pointer, the table data can be retrieved from the program memory using the " tabrd [m]" or "tabrdl [m]" instructions, respectively. when the instruction is executed, the lower order table byte from the program memory will be transferred to the user defned data memory register [m] as specified in the instruction. the higher order table data byte from the program memory will be transferred to the tblh special register. the accompanying diagram illustrates the addressing data fow of the look-up table.
rev. 1.00 ?? de?e??e? 01? ?01? rev. 1.00 ?3 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom last page o? tbhp registe? tblp registe? p?og?a? me?o?y tblh registe? use? sele?ted registe? add?ess data 16 ?its data high byte data low byte table program example the following example shows how the table pointer and table data is defned and retrieved from the microcontroller. this example uses raw table data located in the program memory which is stored there using the org statement. the value at this org statement is "1f00h" which refers to the start address of the last page within the 8k program memory of the device. the table pointer is setup here to have an initial value of "06h". this will ensure that the frst data read from the data table will be at the program memory address "1f06h" or 6 locations after the start of the last page. note that the value for the table pointer is referenced to the frst address of the specifc page pointed by the tbhp register if the "tabrd [m]" instruction is being used. the high byte of the table data which in this case is equal to zero will be transferred to the tblh register automatically when the "tabrd [m]" instruction is executed. because the tblh register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and interrupt service routine use table read instructions. if using the table read instructions, the interrupt service routines may change the value of the tblh and subsequently cause errors if used again by the main routine. as a rule it is recommended that simultaneous use of the table read instructions should be avoided. however, in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. note that all table related instructions require two instruction cycles to complete their operation. table read program example tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : mov a,06h ; initialise low table pointer - note that this address is referenced mov tblp,a ; to the last page or the page that tbhp pointed mov a,1fh ; initialise high table pointer mov tbhp,a : tabrd tempreg1 ; transfers value in table referenced by table pointer data at program ; memory address "1f06h" transferred to tempreg1 and tblh dec tblp ; reduce value of table pointer by one tabrd tempreg2 ; transfers value in table referenced by table pointer ; data at program memory address "1f05h" transferred to ; tempreg2 and tblh in this example the data "1ah" is ; transferred to tempreg1 and data "0fh" to register tempreg2 : org 1f00h ; sets initial address of program memory dc 00ah, 00bh, 00ch, 00dh, 00eh, 00fh, 01ah, 01bh :
rev. 1.00 ?4 de?e??e? 01? ?01? rev. 1.00 ?5 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom in circuit programming C icp the provision of flash type program memory provides the user with a means of convenient and easy upgrades and modifcations to their programs on the same device. as an additional convenience, holtek has provided a means of programming the microcontroller in- circuit using a 4-pin interface. this provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller, and then programming or upgrading the program at a later stage. this enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and re- insertion of the device. the holtek flash mcu to writer programming pin correspondence table is as follows: holtek write pins mcu programming pins function icpda pa0 p?og?a??ing se?ial data/add?ess icpck pa ? p?og?a??ing clo?k vdd vdd powe? supply vss vss g?ound the program memory and eeprom data memory can be programmed serially in-circuit using this 4-wire interface. data is downloaded and uploaded serially on a single pin with an additional line for the clock. two additional lines are required for the power supply. the technical details regarding the in-circuit programming of the device are beyond the scope of this document and will be supplied in supplementary literature. during the programming process, the user must take care of the icpda and icpck pins for data and clock programming purposes to ensure that no other outputs are connected to these two pins. * * w?ite?_vdd icpda icpck w?ite?_vss to othe? ci??uit vdd pa0 pa? vss w?ite? conne?to? signals mcu p?og?a??ing pins note: * may be resistor or capacitor. the resistance of * must be greater than 1 k or the capacitance of * must be less than 1nf.
rev. 1.00 ?4 de?e??e? 01? ?01? rev. 1.00 ?5 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom on-chip debug support C ocds there is an ev chip named ht66v019 which is used to emulate the HT66F019 device. the ev chip device also provides an "on-chip debug" function to debug the real mcu device during the development process. the ev chip and the real mcu device are almost functionally compatible except for "on-chip debug" function. users can use the ev chip device to emulate the real chip device behavior by connecting the ocdsda and ocdsck pins to the holtek ht-ide development tools. the ocdsda pin is the ocds data/address input/output pin while the ocdsck pin is the ocds clock input pin. when users use the ev chip for debugging, other functions which are shared with the ocdsda and ocdsck pins in the device will have no effect in the ev chip. however, the two ocds pins which are pin-shared with the icp programming pins are still used as the flash memory programming pins for icp. for more detailed ocds information, refer to the corresponding document named "holtek e-link for 8-bit mcu ocds users guide". holtek e-link pins ev chip pins pin description ocdsda ocdsda on-chip de?ug suppo?t data/add?ess input/output ocdsck ocdsck on-chip de?ug suppo?t clo?k input vdd vdd powe? supply vss vss g?ound
rev. 1.00 ?6 de?e??e? 01? ?01? rev. 1.00 ?? de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom data memory the data memory is a volatile area of 8-bit wide ram internal memory and is the location where temporary information is stored. structure divided into two areas , the frst of these is an area of ram, known as the special function data memory. here are located registers which are necessary for correct operation of the device. many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. the second area of data memory is known as the general purpose data memory, which is reserved for general purpose use. all locations within this area are read and write accessible under program control. the overall data memory is subdivided into two banks. the special purpose data memory registers are accessible in all banks, with the exception of the eec register at address 40h, which is only accessible in bank 1. switching between the different data memory banks is achieved by setting the bank pointer to the correct value. the start address of the data memory for the device is the address 00h. special purpose data memory general purpose data memory located banks capacity bank: address 0~1: 00h~?fh ex?ept eec ?egiste? (eec@40h in bank 1 only) ?568 0: 80h~ffh 1: 80h~ffh 00h ffh spe?ial pu?pose data me?o?y gene?al pu?pose data me?o?y bank 0 eec at 40h in bank 1 only bank 1 ?fh 80h data memory structure general purpose data memory all microcontroller programs require an area of read/write memory where temporary data can be stored and retrieved for use later. it is this area of ram memory that is known as general purpose data memory. this area of data memory is fully accessible by the user programing for both reading and writing operations. by using the bit operation instructions individual bits can be set or reset under program control giving the user a large range of fexibility for bit manipulation in the data memory. special purpose data memory this area of data memory is where registers, necessary for the correct operation of the microcontroller, are stored. most of the registers are both readable and writeable but some are protected and are readable only, the details of which are located under the relevant special function register section. note that for locations that are unused, any read instruction to these addresses will return the value "00h".
rev. 1.00 ?6 de?e??e? 01? ?01? rev. 1.00 ?? de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom 00h 01h 0?h 03h 04h 05h 06h 0?h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 1?h 13h 14h 15h 16h 1?h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh bank 0 bank 1 bank 0 30h 31h 3?h 33h 34h 35h 36h 3?h 38h 39h 3ah 3bh 3ch 3dh 3eh 3fh 40h 41h 4?h 43h 44h 45h 46h 4?h 48h 49h 4ah 4bh 4ch 4dh 4eh 4fh bank 1 iar0 mp0 iar1 mp1 bp acc pcl tblp tblh status smod lvdc integ intc0 intc1 mfi1 mfi? pa pac papu pawu tmpc sadol sadoh wdtc tbc ctrl eea eed : unused? ?ead as 00h. usr ucr1 ucr? brg txr_rxr tbhp ?0h ?1h ??h ?3h ?4h ?5h ?6h ??h ?8h ?9h ?ah ?bh ?ch ?dh ?eh ?fh sadc0 sadc1 pb pbc pbpu acerl 50h 51h 5?h 53h 54h 55h 56h 5?h 58h 59h 5ah 5bh 5ch 5dh 5eh 5fh lvrc intc? mfi0 ctmc1 ctmc0 stmc1 stmdl ctmdl ctmdh ctmal ctmrp stmc0 stmdh stmal stmrp ptmc0 ptmc1 stmah ctmah ptmdh ptmdl ptmal ptmah ptmrpl cpc ptmrph eec ifs simc?/sima simtoc pc pcc simc0 simc1 simd 60h 61h 6?h 63h 64h 65h 66h 6?h 68h 69h 6ah 6bh 6ch 6dh 6eh 6fh ?0h ?1h ??h ?3h ?4h ?5h ?6h ??h ?8h ?9h ?ah ?bh ?ch ?dh ?eh ?fh pcpu special purpose data memory structure
rev. 1.00 ?8 de?e??e? 01? ?01? rev. 1.00 ?9 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom special function register description most of the special function register details will be described in the relevant functional sections ; however several registers require a separate description in this section. indirect addressing register C iar0, iar1 the indirect addressing registers, iar0 and iar1, although having their locations in normal ram register space, do not actually physically exist as normal registers. the method of indirect addressing for ram data manipulation uses these indirect addressing registers and memory pointers, in contrast to direct memory addressing, where the actual memory address is specifed. actions on the iar0 and iar1 registers will result in no actual read or write operation to these registers but rather to the memory location specifed by their corresponding memory pointers, mp0 or mp1. acting as a pair, iar0 and mp0 can together access data from bank 0 while the iar1 and mp1 register pair can access data from any bank. as the indirect addressing registers are not physically implemented, reading the indirect addressing registers indirectly will return a result of "00h" and writing to the registers indirectly will result in no operation. memory pointers C mp0, mp1 two memory pointers, known as mp0 and mp1 are provided. these memory pointers are physically implemented in the data memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. when any operation to the relevant indirect addressing registers is carried out, the actual address that the microcontroller is directed to, is the address specifed by the related memory pointer. mp0, together with indirect addressing register, iar0, are used to access data from bank 0, while mp1 and iar1 are used to access data from all banks according to bp register. direct addressing can only be used with bank 0, all other banks must be addressed indirectly using mp1 and iar1. the following example shows how to clear a section of four data memory locations already defned as locations adres1 to adres4. indirect addressing program example data .section data adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 code org 00h start: mov a,04h ; setup size of block mov block,a mov a,offset adres1 ; accumulator loaded with frst ram address mov mp0,a ; setup memory pointer with frst ram address loop: clr iar0 ; clear the data at address defned by mp0 inc mp0 ; increment memory pointer sdz block ; check if last memory location has been cleared jmp loop continue: the important point to note here is that in the example shown above, no reference is made to specifc data memory addresses.
rev. 1.00 ?8 de?e??e? 01? ?01? rev. 1.00 ?9 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom bank pointer C bp for this device, the data memory is divided into two banks, bank 0 and bank 1. selecting the required data memory area is achieved using the bank pointer. bit 0 of the bank pointer is used to select data memory banks 0~1. the data memory is initialised to bank 0 after a reset, except for a wdt time-out reset in the sleep or idle mode, in which case, the data memory bank remains unaffected. directly addressing the data memory will always result in bank 0 being accessed irrespective of the value of the bank pointer. accessing data from banks other than bank 0 must be implemented using indirect addressing. ? bp register bit 7 6 5 4 3 2 1 0 na?e dmbp0 r/w r/w por 0 bit 7~1 unimplemented, read as "0" bit 0 dmbp0 : select data memory banks 0: bank 0 1: bank 1 accumulator C acc the accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the alu. the accumulator is the place where all intermediate results from the alu are stored. without the accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the data memory resulting in higher programming and timing overheads. data transfer operations usually involve the temporary storage function of the accumulator; for example, when transferring data between one user defined register and another, it is necessary to do this by passing the data through the accumulator as no direct transfer between two registers is permitted. program counter low register C pcl to provide additional program control functions, the low byte of the program counter is made accessible to programmers by locating it within the special purpose area of the data memory. by manipulating this register, direct jumps to other program locations are easily implemented. loading a value directly into this pcl register will cause a jump to the specifed program memory location, however, as the register is only 8-bit wide, only jumps within the current program memory page are permitted. when such operations are used, note that a dummy cycle will be inserted. look-up table registers C tblp, tbhp, tblh these three special function registers are used to control operation of the look-up table which is stored in the program memory. tblp and tbhp are the table pointers and indicate the location where the table data is located. their value must be setup before any table read commands are executed. their value can be changed, for example using the "inc" or "dec" instructions, allowing for easy table data pointing and reading. tblh is the location where the high order byte of the table data is stored after a table read data instruction has been executed. note that the lower order table data byte is transferred to a user defned location.
rev. 1.00 30 de?e??e? 01? ?01? rev. 1.00 31 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom status register C status this 8-bit register contains the zero fag (z), carry fag (c), auxiliary carry fag (ac), overfow fag (ov), power down fag (pdf), and watchdog time-out fag (to). these arithmetic/logical operation and system management fags are used to record the status and operation of the microcontroller. with the exception of the to and pdf fags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the to or pdf fag. in addition, operations related to the status register may give different results due to the different instruction operations. the to fag can be affected only by a system power-up, a wdt time-out or by executing the "clr wdt" or "halt" instruction. the pdf fag is affected only by executing the "halt" or "clr wdt" instruction or during a system power-up. the z, ov, ac and c fags generally refect the status of the latest operations. ? c is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise c is cleared. c is also affected by a rotate through carry instruction. ? ac is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. ? z is set if the result of an arithmetic or logical operation is zero; otherwise z is cleared. ? ov is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. ? pdf is cleared by a system power-up or executing the "clr wdt" instruction. pdf is set by executing the "halt" instruction. ? to is cleared by a system power-up or executing the "clr wdt" or "halt" instruction. to is set by a wdt time-out. in addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically. if the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it.
rev. 1.00 30 de?e??e? 01? ?01? rev. 1.00 31 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom ? status register bit 7 6 5 4 3 2 1 0 na?e to pdf ov z ac c r/w r r r/w r/w r/w r/w por 0 0 x x x x "x": unknown bit 7~6 unimplemented, read as "0" bit 5 to : watchdog time-out fag 0: after power up or executing the "clr wdt" or "halt" instruction 1: a watchdog time-out occurred bit 4 pdf : power down fag 0: after power up or executing the "clr wdt" instruction 1: by executing the "halt" instruction bit 3 ov : overfow fag 0: no overfow 1: an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa bit 2 z : zero fag 0: the result of an arithmetic or logical operation is not zero 1: the result of an arithmetic or logical operation is zero bit 1 ac : auxiliary fag 0: no auxiliary carry 1: an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction bit 0 c : carry fag 0: no carry-out 1: an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation the "c" fag is also affected by a rotate through carry instruction.
rev. 1.00 3? de?e??e? 01? ?01? rev. 1.00 33 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom eeprom data memory this device contains an area of internal eeprom data memory. eeprom is by its nature a non- volatile form of re-programmable memory, with data retention even when its power supply is removed. by incorporating this kind of data memory, a whole new host of application possibilities are made available to the designer. the availability of eeprom storage allows information such as product identifcation numbers, calibration values, specifc user data, system setup data or other product information to be stored directly within the product microcontroller. the process of reading and writing data to the eeprom memory has been reduced to a very trivial affair. eeprom data memory structure the eeprom data memory capacity is 64 8 bits for the device. unlike the program memory and ram data memory, the eeprom data memory is not directly mapped into memory space and is therefore not directly addressable in the same way as the other types of memory. read and write operations to the eeprom are carried out in single byte operations using an address and a data register in bank 0~bank1 and a single control register in bank 1. eeprom registers three registers control the overall operation of the internal eeprom data memory. these are the address register, eea, the data register, eed and a single control register, eec. as both the eea and eed registers are accessable in all banks, they can be directly accessed in the same way as any other special function register which are located in bank 0. the eec register, however, only being located in bank 1 , can be read from or written to indire ctly using the mp1 memory pointer and indirect addressing register, iar1. because the eec control register is located at address 40h in bank 1, the mp1 memory pointer must frst be set to the value 40h and the bank pointer register, bp, set to the value, 01h, before any operations on the eec register are executed. register name bit 7 6 5 4 3 2 1 0 eea eea5 eea4 eea3 eea? eea1 eea0 eed d? d6 d5 d4 d3 d? d1 d0 eec wren wr rden rd eeprom register list ? eea register bit 7 6 5 4 3 2 1 0 na?e eea5 eea4 eea3 eea? eea1 eea0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 unimplemented, read as "0" bit 5~0 eea5~eea0 : data eeprom address data eeprom address bit 5~bit 0
rev. 1.00 3? de?e??e? 01? ?01? rev. 1.00 33 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom ? eed register bit 7 6 5 4 3 2 1 0 na?e d? d6 d5 d4 d3 d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 d7~d0 : data eeprom data data eeprom data bit 7~bit 0 ? eec register bit 7 6 5 4 3 2 1 0 na?e wren wr rden rd r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~4 unimplemented, read as "0" bit 3 wren : data eeprom write enable 0: disable 1: enable this is the data eeprom write enable bit which must be set high before data eeprom write operations are carried out. clearing this bit to zero will inhibit data eeprom write operations. bit 2 wr : eeprom write control 0: write cycle has fnished 1: activate a write cycle this is the data eeprom write control bit and when set high by the application program will activate a write cycle. this bit will be automatically reset to zero by the hardware after the write cycle has fnished. setting this bit high will have no effect if the wren has not frst been set high. bit 1 rden : data eeprom read enable 0: disable 1: enable this is the data eeprom read enable bit which must be set high before data eeprom read operations are carried out. clearing this bit to zero will inhibit data eeprom read operations. bit 0 rd : eeprom read control 0: read cycle has fnished 1: activate a read cycle this is the data eeprom read control bit and when set high by the application program will activate a read cycle. this bit will be automatically reset to zero by the hardware after the read cycle has fnished. setting this bit high will have no effect if the rden has not frst been set high. note: the wren, wr, rden and rd cannot be set high at the same time in one instruction. the wr and rd cannot be set high at the same time.
rev. 1.00 34 de?e??e? 01? ?01? rev. 1.00 35 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom reading data from the eeprom to read data from the eeprom, the read enable bit, rden, in the eec register must frst be set high to enable the read function. the eeprom address of the data to be read must then be placed in the eea register. if the rd bit in the eec register is now set high, a read cycle will be initiated. setting the rd bit high will not initiate a read operation if the rden bit has not been set. when the read cycle terminates, the rd bit will be automatically cleared to zero, after which the data can be read from the eed register. the data will remain in the eed register until another read or write operation is executed. the application program can poll the rd bit to determine when the data is valid for reading. writing data to the eeprom to write data to the eeprom, the eeprom address of the data to be written must frst be placed in the eea register and the data placed in the eed register. then the write enable bit, wren, in the eec register must first be set high to enable the write function. after this, the wr bit in the eec register must be immediately set high to initiate a write cycle. these two instructions must be executed consecutively. the global interrupt bit emi should also first be cleared before implementing any write operations, and then set again after the write cycle has started. note that setting the wr bit high will not initiate a write cycle if the wren bit has not been set. as the eeprom write cycle is controlled using an internal timer whose operation is asynchronous to microcontroller system clock, a certain time will elapse before the data will have been written into the eeprom. detecting when the write cycle has fnished can be implemented either by polling the wr bit in the eec register or by using the eeprom interrupt. when the write cycle terminates, the wr bit will be automatically cleared to zero by the microcontroller, informing the user that the data has been written to the eeprom. the application program can therefore poll the wr bit to determine when the write cycle has ended. write protection protection against inadvertent write operation is provided in several ways. after the device is powered-on the write enable bit in the control register will be cleared preventing any write operations. also at power-on the bank pointer, bp, will be reset to zero, which means that data memory bank 0 will be selected. as the eeprom control register is located in bank 1, this adds a further measure of protection against spurious write operations. during normal program operation, ensuring that the write enable bit in the control register is cleared will safeguard against incorrect write operations. eeprom interrupt the eeprom write interrupt is generated when an eeprom write cycle has ended. the eeprom interrupt must frst be enabled by setting the dee bit in the relevant interrupt register. however, as the eeprom is contained within a multi-function interrupt, the associated multi-function interrupt enable bit must also be set. when an eeprom write cycle ends, the def request flag and its associated multi-function interrupt request fag will both be set. if the global, eeprom and multi- function interrupts are enabled and the stack is not full, a jump to the associated multi-function interrupt vector will take place. when the interrupt is serviced only the multi-function interrupt fag will be automatically reset, the eeprom interrupt fag must be manually reset by the application program.
rev. 1.00 34 de?e??e? 01? ?01? rev. 1.00 35 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom programming considerations care must be taken that data is not inadvertently written to the eeprom. protection can be enhanced by ensuring that the write enable bit is normally cleared to zero when not writing. also the bank pointer could be normally cleared to zero as this would inhibit access to bank 1 where the eeprom control register exist. although certainly not necessary, consideration might be given in the application program to the checking of the validity of new write data by a simple read back process. when writing data the wr bit must be set high immediately after the wren bit has been set high, to ensure the write cycle executes correctly. the global interrupt bit emi should also be cleared before a write cycle is executed and then re-enabled after the write cycle starts. note that the device should not enter the idle or sleep mode until the eeprom read or write operation is totally complete. otherwise, the eeprom read or write operation will fail. programming examples reading data from the eeprom C polling method mov a, eeprom_adres ; user defned address mov eea, a mov a, 040h ; setup memory pointer mp1 mov mp1, a ; mp1 points to eec register mov a, 01h ; setup bank pointer mov bp, a set iar1.1 ; set rden bit, enable read operations set iar1.0 ; start read cycle - set rd bit back: sz iar1.0 ; check for read cycle end jmp back clr iar1 ; disable eeprom read/write clr bp mov a, eed ; move read data to register mov read_data, a writing data to the eeprom C polling method mov a, eeprom_adres ; user defned address mov eea, a mov a, eeprom_data ; user defned data mov eed, a mov a, 040h ; setup memory pointer mp1 mov mp1, a ; mp1 points to eec register mov a, 01h ; setup bank pointer mov bp, a clr emi set iar1.3 ; set wren bit, enable write operations set iar1.2 ; start write cycle - set wr bit C executed immediately ; after set wren bit set emi back: sz iar1.2 ; check for write cycle end jmp back clr iar1 ; disable eeprom read/write clr bp
rev. 1.00 36 de?e??e? 01? ?01? rev. 1.00 3? de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom oscillators various oscillator options offer the user a wide range of functions according to their various application requirements. the flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. oscillator selections and operation are selected through a combination of confguration options and registers. oscillator overview in addition to being the source of the main system clock the oscillators also provide clock sources for the watchdog timer and time base interrupts. external oscillators requiring some external components as well as fully integrated internal oscillators, requiring no external components, are provided to form a wide range of both fast and slow system oscillators. all oscillator options are selected through the configuration options. the higher frequency oscillators provide higher performance but carry with it the disadvantage of higher power requirements, while the opposite is of course true for the lower frequency oscillators. with the capability of dynamically switching between fast and slow system clock, the device has the flexibility to optimize the performance/ power ratio, a feature especially important in power sensitive portable applications. type name frequency pins high speed exte?nal c?ystal hxt 400khz~16mhz osc1/osc? high speed inte?nal rc hirc 8/1?/16mhz low speed exte?nal c?ystal lxt 3?.?68khz xt1/xt? low speed inte?nal rc lirc 3?khz oscillator types system clock confgurations there are four methods of generating the system clock, two high speed oscillator and two low speed oscillator. the high speed oscillators are the external crystal/ceramic oscillator, hxt, and the internal 8/12/16mhz rc oscillator , hirc . the two low speed oscillators are the internal 32khz rc oscillator, lirc, and the external 32.768khz crystal oscillator, lxt. selecting whether the low or high speed oscillator is used as the system oscillator is implemented using the hlclk bit and cks2~cks0 bits in the smod register and as the system clock can be dynamically selected. the actual source clock used for the high speed and low speed oscillators is chosen via confguration options . the frequency of the slow speed or high speed system clock is also determined using the hlclk bit and cks2~cks0 bits in the smod register. note that two oscillator selections must be made namely one high speed and one low speed system oscillators. it is not possible to choose a no- oscillator selection for either the high or low speed oscillator. the osc1/osc2 and xt1/xt2 pins are used to connect the external components for the external crystal.
rev. 1.00 36 de?e??e? 01? ?01? rev. 1.00 3? de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom hxt hirc f h 6-stage p?es?ale? high speed os?illato?s configu?ation option hlclk? cks?~cks0 ?its f h /? f h /4 f h /8 f h /16 f h /3? f h /64 f sub f sub fast wake-up f?o? sleep mode o? idle mode cont?ol (fo? hxt only) f sys high speed os?illato?s lirc lxt low speed os?illato?s configu?ation option low speed os?illato?s system clock confgurations external crystal/ceramic oscillator C hxt the external crystal/ceramic system oscillator is one of the high frequency oscillator choices, which is selected via configuration option. for most crystal oscillator configurations, the simple connection of a crystal across osc1 and osc2 will create the necessary phase shift and feedback for oscillation, without requiring external capacitors. however, for some crystal types and frequencies, to ensure oscillation, it may be necessary to add two small value capacitors, c1 and c2. using a ceramic resonator will usually require two small value capacitors, c1 and c2, to be connected as shown for oscillation to occur. the values of c1 and c2 should be selected in consultation with the crystal or resonator manufacturers specifcation. for oscillator stability and to minimise the effects of noise and crosstalk, it is important to ensure that the crystal and any associated resistors and capacitors along with interconnecting lines are all located as close to the mcu as possible. note: 1. r p is no??ally not ?equi?ed. c1 and c? a?e ?equi?ed. ?. although not shown osc1/o sc? pins have a pa?asiti? ?apa?itan?e of a?ound ?pf. to inte?nal ?i??uits internal oscillator circuit c1 c? osc1 osc? r f r p crystal/resonator oscillator C hxt
rev. 1.00 38 de?e??e? 01? ?01? rev. 1.00 39 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom crystal oscillator c1 and c2 values crystal frequency c1 c2 16mhz 0pf 0pf 1?mhz 0pf 0pf 8mhz 0pf 0pf 4mhz 0pf 0pf 1mhz 100pf 100pf note: c1 and c? values a?e fo? guidan? e only. crystal recommended capacitor values internal rc oscillator C hirc the internal rc oscillator is a fully integrated system oscillator requiring no external components. the internal rc oscillator has three fixed frequencies of 8mhz, 12mhz and 16mhz. device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. as a result, at a power supply of either 3v or 5v and at a temperature of 25c degrees, the fxed oscillation frequency of 8mhz, 12mhz or 16mhz will have a tolerance within 1%. note that if this internal system clock option is selected, as it requires noexternal pins for its operation, i/o pins are free for use as normal i/o pins. external 32.768khz crystal oscillator C lxt the external 32.768khz crystal system oscillator is one of the low frequency oscillator choices, which is selected via confguration option. this clock source has a fxed frequency of 32.768khz and requires a 32.768khz crystal to be connected between pins xt1 and xt2. the external resistor and capacitor components connected to the 32.768khz crystal are necessary to provide oscillation. for applications where precise frequencies are essential, these components may be required to provide frequency compensation due to different crystal manufacturing tolerances. during power-up there is a time delay associated with the lxt oscillator waiting for it to start-up. when the microcontroller enters the sleep or idle mode, the system clock is switched off to stop microcontroller activity and to conserve power. however, in many microcontroller applications it may be necessary to keep the internal timers operational even when the microcontroller is in the sleep or idle mode. to do this, another clock, independent of the system clock, must be provided. however, for some crystals, to ensure oscillation and accurate frequency generation, it is necessary to add two small value external capacitors, c1 and c2. the exact values of c1 and c2 should be selected in consultation with the crystal or resonator manufacturers specification. the external parallel feedback resistor, r p , is required. the pin-shared software control bits determine if the xt1/xt2 pins are used for the lxt oscillator or as i/o or other pin-shared functional pins. ? if the lxt oscillator is not used for any clock source, the xt1/xt2 pins can be used as normal i/o or other pin-shared functional pins. ? if the lxt oscillator is used for any clock source, the 32.768 khz crystal should be connected to the xt1/xt2 pins. for oscillator stability and to minimise the effects of noise and crosstalk, it is important to ensure that the crystal and any associated resistors and capacitors along with interconnecting lines are all located as close to the mcu as possible.
rev. 1.00 38 de?e??e? 01? ?01? rev. 1.00 39 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom note: 1. r p ? c1 and c? a?e ?equi?ed. ?. although not shown pins have a pa?asiti? ?apa?itan?e of a?ound ?pf. to inte?nal ?i??uits internal oscillator circuit c1 c? xt1 xt? r p 3?.?68khz inte?nal rc os?illato? external lxt oscillator lxt oscillator c1 and c2 values crystal frequency c1 c2 3?.?68khz 10pf 10pf note: 1. c1 and c? values a?e fo? guidan? e only. ?. r p =5m ~10m is recommended. 32.768khz crystal recommended capacitor values lxt oscillator low power function the lxt oscillator can function in one of two modes, the quick start mode and the low power mode. the mode selection is executed using the lxtlp bit in the tbc register. lxtlp bit lxt mode 0 qui?k sta?t 1 low-powe? after power on, the lxtlp bit will be automatically cleared to zero ensuring that the lxt oscillator is in the quick start operating mode. in the quick start mode the lxt oscillator will power up and stabilise quickly. however, after the lxt oscillator has fully powered up it can be placed into the low-power mode by setting the lxtlp bit high. the oscillator will continue to run but with reduced current consumption, as the higher current consumption is only required during the lxt oscillator start-up. in power sensitive applications, such as battery applications, where power consumption must be kept to a minimum, it is therefore recommended that the application program sets the lxtlp bit high about 2 seconds after power-on. it should be noted that, no matter what condition the lxtlp bit is set to, the lxt oscillator will always function normally, the only difference is that it will take more time to start up if in the lowpower mode. internal 32khz oscillator C lirc the internal 32khz system oscillator is one of the low frequency oscillator choices, which is selected via confguration option. it is a fully integrated rc oscillator with a typical frequency of 32khz at 5v , requiring no external components for its implementation. device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. as a result, at a power supply of 5v and at a temperature of 25c degrees, the fxed oscillation frequency of 32khz will have a tolerance within 10%. supplementary oscillators the low speed oscillators, in addition to providing a system clock source are also used to provide a clock source to two other device functions. these are the watchdog timer and the time base interrupts.
rev. 1.00 40 de?e??e? 01? ?01? rev. 1.00 41 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom operating modes and system clocks present day applications require that their microcontrollers have high performance but often still demand that they consume as little power as possible, conficting requirements that are especially true in battery powered portable applications. the fast clocks required for high performance will by their nature increase current consumption and of course vice-versa, lower speed clocks reduce current consumption. as holtek has provided this device with both high and low speed clock sources and the means to switch between them dynamically, the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. system clocks the device has many different clock sources for both the cpu and peripheral function operation. by providing the user with a wide range of clock options using confguration options and register programming, a clock system can be confgured to obtain maximum application performance. the main system clock, can come from either a high frequency f h or low frequency f sub source, and is selected using the hlclk bit and cks2~cks0 bits in the smod register. the high speed system clock can be sourced from either an hxt or hirc oscillator, selected via a confguration option. the low speed system clock source can be sourced from internal clock f sub . if f sub is selected then it can be sourced by either the lxt or lirc oscillator, selected via a confguration option. the other choice, which is a divided version of the high speed system oscillator has a range of f h /2~f h /64. there are two additional internal clocks for the peripheral circuits, the substitute clock, f sub , and the time base clock, f tbc . each of these internal clocks is sourced by either the lxt or lirc oscillator, selected via configuration options. the f sub clock is used to provide a substitute clock for the microcontroller just after a wake-up has occurred to enable faster wake-up times. hxt hirc lirc low speed os?illato?s f h 6-stage p?es?ale? high speed os?illato?s configu?ation option hlclk? cks?~cks0 ?its f h /? f h /4 f h /8 f h /16 f h /3? f h /64 f sub fast wake-up f?o? sleep o? idle mode cont?ol (fo? hxt only) f sys lxt high speed os?illato?s low speed os?illato?s configu?ation option f sys /4 ti?e base f tb tbck f tbc wat?hdog ti?e? f s f sub device clock confgurations note: when the system clock source f sys is switched to f sub from f h , the high speed oscillator can be stopped to conserve the power. thus there is no f h ~f h /64 for peripheral circuit to use.
rev. 1.00 40 de?e??e? 01? ?01? rev. 1.00 41 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom system operation modes there are six different modes of operation for the microcontroller, each one with its own special characteristics and which can be chosen according to the specific performance and power requirements of the application. there are two modes allowing normal operation of the microcontroller, the fast mode and slow mode. the remaining four modes, the sleep0, sleep1, idle0 and idle1 mode are used when the microcontroller cpu is switched off to conserve power. operation mode description cpu f sys f sub f s f tbc fast on f h ~f h /64 on on on slow on f sub on on on idle0 off off on on on idle1 off on on on on sleep0 off off off off off sleep1 off off on on off fast mode as the name suggests this is one of the main operating modes where the microcontroller has all of its functions operational and where the system clock is provided by one of the high speed oscillators. this mode operates allowing the microcontroller to operate normally with a clock source will come from one of the high speed oscillators, either the hxt or hirc oscillator. the high speed oscillator will however frst be divided by a ratio ranging from 1 to 64, the actual ratio being selected by the cks2~cks0 and hlclk bits in the smod register. although a high speed oscillator is used, running the microcontroller at a divided clock ratio reduces the operating current. slow mode this is also a mode where the microcontroller operates normally although now with a slower speed clock source. the clock source used will be from one of the low speed oscillators, either the lxt or the lirc. running the microcontroller in this mode allows it to run with much lower operating currents. in the slow mode, the f h is off. sleep0 mode the sleep mode is entered when an halt instruction is executed and when the idlen bit in the smod register be low. in the sleep0 mode the cpu will be stopped, and the f sub and f s clocks will be stopped too, and the watchdog timer function is disabled. in this mode, the lvden is must set to "0". if the lvden is set to "1", it wont enter the sleep0 mode. sleep1 mode the sleep mode is entered when an halt instruction is executed and when the idlen bit in the smod register be low. in the sleep1 mode the cpu will be stopped. however the f sub and f s clocks will continue to operate if the lvden is "1" or the watchdog timer function is enabled and if its clock source is chosen via confguration option to come from the f sub . idle0 mode the idle0 mode is entered when a halt instruction is executed and when the idlen bit in the smod register is high and the fsyson bit in the ctrl register is low. in the idle0 mode the system oscillator will be inhibited from driving the cpu but some peripheral functions will remain operational such as the watchdog timer and tms. in the idle0 mode, the system oscillator will be stopped.
rev. 1.00 4? de?e??e? 01? ?01? rev. 1.00 43 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom idle1 mode the idle1 mode is entered when an halt instruction is executed and when the idlen bit in the smod register is high and the fsyson bit in the ctrl register is high. in the idle1 mode the system oscillator will be inhibited from driving the cpu but may continue to provide a clock source to keep some peripheral functions operational such as the watchdog timer and tms. in the idle1 mode, the system oscillator will continue to run, and this system oscillator may be high speed or low speed system oscillator. control registers a single register, smod, is used for overall control of the internal clocks within the device. ? smod register bit 7 6 5 4 3 2 1 0 na?e cks? cks1 cks0 fsten lto hto idlen hlclk r/w r/w r/w r/w r/w r r r/w r/w por 0 0 0 0 0 0 1 1 bit 7~5 cks2~cks0 : system clock selection when hlclk is "0" 000: f (f lxt or f lirc ) 001: f (f lxt or f lirc ) 010: f /64 011: f /32 100: f /16 101: f /8 110: f /4 111: f /2 these three bits are used to select which clock is used as the system clock source. in addition to the system clock source, which can be either the lxt or lirc, a divided version of the high speed system oscillator can also be chosen as the system clock source. bit 4 fsten : fast wake-up control (only for hxt) 0: disable 1: enable this is the fast wake-up control bit which determines if the f clock source is initially used after the device wakes up. when the bit is high, the f clock source can be used as a temporary system clock to provide a faster wake up time as the f clock is available. bit 3 lto : low system oscillator ready fag 0: not ready 1: ready this is the low speed system oscillator ready fag which indicates when the low speed system oscillator is stable after power on reset or a wake-up has occurred. the fag will be low when in the sleep0 mode but after a wake-up has occurred, the fag will change to a high level after 128 clock cycles if the lxt oscillator is used and 1~2 clock cycles if the lirc oscillator is used. bit 2 hto : high system oscillator ready fag 0: not ready 1: ready this is the high speed system oscillator ready fag which indicates when the high speed system oscillator is stable. this flag is cleared to "0" by hardware when the device is powered on and then changes to a high level after the high speed system oscillator is stable. therefore this fag will always be read as "1" by the application program after device power-on. the fag will be low when in the sleep or idle0 mode but after a wake- up has occurred, the fag will change to a high level after 128 clock cycles if the hxt oscillator is used and after 15~16 clock cycles if the hirc oscillator is used
rev. 1.00 4? de?e??e? 01? ?01? rev. 1.00 43 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom bit 1 idlen : idle mode control 0: disable 1: enable this is the idle mode control bit and determines what happens when the halt instruction is executed. if this bit is high, when a halt instruction is executed, the device will enter the idle mode. in the idle mode the cpu will stop running but the system clock will continue to keep the peripheral functions operational, if the fsyson bit is high. if the fsyson bit is low, the cpu and the system clock will all stop in idle0 mode. if the bit is low, the device will enter the sleep mode when a halt instruction is executed. bit 0 hlclk : system clock selection 0: f h /2~f h /64 or f sub 1: f h this bit is used to select if the f h clock or the f h /2~f h /64 or f sub clock is used as the system clock. when the bit is high the f h clock will be selected and if low the f h /2~f h /64 or f sub clock will be selected. when system clock switches from the f h clock to the f sub clock and the f h clock will be automatically switched off to conserve power. to minimise power consumption the device can enter the sleep or idle0 mode, where the system clock source to the device will be stopped. however when the device is woken up again, it can take a considerable time for the original system oscillator to restart, stabilise and allow normal operation to resume. to ensure the device is up and running as fast as possible a fast wake-up function is provided, which allows f sub , namely either the lxt or lirc oscillator, to act as a temporary clock to frst drive the system until the original system oscillator has stabilised. as the clock source for the fast wake-up function is f sub , the fast wake-up function is only available in the sleep1 and idle0 modes. when the device is woken up from the sleep0 mode, the fast wake-up function has no effect because the f sub clock is stopped. the fast wake-up enable/disable function is controlled using the fsten bit in the smod register. if the hxt oscillator is selected as the fast mode system clock, and if the fast wake-up function is enabled, then it will take one to two t sub clock cycles of the lirc or lxt oscillator for the system to wake-up. the system will then initially run under the f sub clock source until 128 hxt clock cycles have elapsed, at which point the hto fag will switch high and the system will switch over to operating from the hxt oscillator. if the hirc oscillator or lirc oscillator is used as the system oscillator then it will take 15~16 clock cycles of the hirc or 1~2 cycles of the lirc to wake up the system from the sleep or idle0 mode. the fast wake-up bit, fsten will have no effect in these case s. hxt 0 1? 8 hxt ?y?les 1? 8 hxt ?y?les 1~? hxt ?y?les 1 1? 8 hxt ?y?les 1~? f sub ?y?les (syste? ?uns with f sub frst for 512 hxt ?y?les and then swit?hes ove? to ? un with the hxt ?lo?k) 1~? hxt ?y?les hirc x 15~16 hirc ?y?les 15~16 hirc ?y?les 1~? hirc ?y?les lirc x 1~? lirc ?y?les 1~? lirc ?y?les 1~? lirc ?y?les lxt x 1? 8 lxt ?y?les 1? 8 lxt ?y?les 1~? lxt ?y?les "x": dont ?a?e wake-up ti?es note that if the watchdog timer is disabled, which means that the lxt and lirc are all both off, then there will be no fast wake-up function available when the device wake-up from the sleep0 mode.
rev. 1.00 44 de?e??e? 01? ?01? rev. 1.00 45 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom operating mode switching the device can switch between operating modes dynamically allowing the user to select the best performance/power ratio for the present task in hand. in this way microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. in simple terms, mode switching between the fast mode and slow mode is executed using the hlclk bit and cks2~cks0 bits in the smod register while mode switching from the fast/ slow modes to the sleep/idle modes is executed via the halt instruction. when a halt instruction is executed, whether the device enters the idle mode or the sleep mode is determined by the condition of the idlen bit in the smod register and the fsyson bit in the ctrl register. when the hlclk bit switches to a low level, which implies that clock source is switched from the high speed clock, f h , to the clock source, f h /2~f h /64 or f sub . if the clock is from the f sub , the high speed clock source will stop running to conserve power. when this happens, it must be noted that the f h /16 and f h /64 internal clock sources will also stop running, which may affect the operation of other internal functions such as the tms.the accompamying chart shows what happens when the device moves between the various operating modes. fast f sys =f h ~f h /64 f h on cpu ?un f sys on f tbc on f sub on slow f sys =f sub f sub on cpu ?un f sys on f tbc on f h off idle0 halt inst?u?tion exe?uted cpu stop idlen=1 fsyson=0 f sys off f tbc on f sub on idle1 halt inst?u?tion exe?uted cpu stop idlen=1 fsyson=1 f sys on f tbc on f sub on sleep1 halt inst?u?tion exe?uted f sys off cpu stop idlen=0 f tbc off f sub on wdt on sleep0 halt inst?u?tion exe?uted f sys off cpu stop idlen=0 f tbc off f sub off wdt & lvd off
rev. 1.00 44 de?e??e? 01? ?01? rev. 1.00 45 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom fast mode to slow mode switching when running in the fast mode, which uses the high speed system oscillator, and therefore consumes more power, the system clock can switch to run in the slow mode by set the hlclk bit to "0" and set the cks2~cks0 bits to "000" or "001" in the smod register. this will then use the low speed system oscillator which will consume less power. users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption. the slow mode is sourced from the lxt or the lirc oscillators and therefore requires these oscillators to be stable before full mode switching occurs. this is monitored using the lto bit in the smod register. fast mode slow mode cks?~cks0=00xb & hlck=0 sleep0 mode idlen=0 halt inst?u?tion is exe?uted sleep1 mode idlen=0 halt inst?u?tion is exe?uted idle0 mode idlen=1? fsyson=0 halt inst?u?tion is exe?uted idle1 mode idlen=1? fsyson=1 halt inst?u?tion is exe?uted wdt and lvd a?e all off wdt is on
rev. 1.00 46 de?e??e? 01? ?01? rev. 1.00 4? de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom slow mode to fast mode switching in slow mode the system uses either the lxt or lirc low speed system oscillator. to switch back to the fast mode, where the high speed system oscillator is used, the hlclk bit should be set to "1" or hlclk bit is "0", but cks2~cks0 feld is set to "010", "011", "100", "101", "110" or "111". as a certain amount of time will be required for the high frequency clock to stabilise, the status of the hto bit is checked. the amount of time required for high speed system oscillator stabilization depends upon which high speed system oscillator type is used. fast mode slow mode cks?~cks0=010~111 as hlclk=0 o? hlclk=1 sleep0 mode idlen=0 halt inst?u?tion is exe?uted sleep1 mode idlen=0 halt inst?u?tion is exe?uted idle0 mode idlen=1? fsyson=0 halt inst?u?tion is exe?uted idle1 mode idlen=1? fsyson=1 halt inst?u?tion is exe?uted wdt and lvd a?e all off wdt is on entering the sleep0 mode there is only one way for the device to enter the sleep0 mode and that is to execute the "halt" instruction in the application program with the idlen bit in the smod register equal to "0" and the wdt and lvd both off. when this instruction is executed under the conditions described above, the following will occur: ? the system clock and time base clock will be stopped and the application program will stop at the "halt" instruction. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and stopped no matter if the wdt clock source originates from the f sub clock or from the system clock. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag pdf will be set, and wdt timeout fag to will be cleared.
rev. 1.00 46 de?e??e? 01? ?01? rev. 1.00 4? de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom entering the sleep1 mode there is only one way for the device to enter the sleep1 mode and that is to execute the "halt" instruction in the application program with the idlen bit in the smod register equal to "0" and the wdt is on. when this instruction is executed under the conditions described above, the following will occur: ? the system clock and time base clock will be stopped and the application program will stop at the "halt" instruction, but the wdt will remain with the clock source coming from the f sub clock. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting if the wdt is enabled. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag pdf will be set, and wdt timeout fag to will be cleared. entering the idle0 mode there is only one way for the device to enter the idle0 mode and that is to execute the "halt" instruction in the application program with the idlen bit in the smod register equal to "1" and the fsyson bit in the ctrl register equal to "0". when this instruction is executed under the conditions described above, the following will occur: ? the system clock will be stopped and the application program will stop at the "halt" instruction, but the time base and f sub clocks will be on. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting if the wdt is enabled. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag pdf will be set, and wdt timeout fag to will be cleared. entering the idle1 mode there is only one way for the device to enter the idle1 mode and that is to execute the "halt" instruction in the application program with the idlen bit in the smod register equal to "1" and the fsyson bit in the ctrl register equal to "1". when this instruction is executed under the conditions described above, the following will occur: ? the system clock and the low frequency f sub clocks will be on but the application program will stop at the "halt" instruction. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting if the wdt is enabled. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag pdf will be set, and wdt timeout fag to will be cleared.
rev. 1.00 48 de?e??e? 01? ?01? rev. 1.00 49 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom standby current considerations as the main reason for entering the sleep or idle mode is to keep the current consumption of the device to as low a value as possible, perhaps only in the order of several micro-amps except in the idle1 mode, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised. special attention must be made to the i/o pins on the device. all high-impedance input pins must be connected to either a fxed high or low level as any foating input pins could create internal oscillations and result in increased current consumption. this also applies to the device which has different package types, as there may be unbonbed pins. these must either be setup as outputs or if setup as inputs must have pull-high resistors connected. care must also be taken with the loads, which are connected to i/o pins, which are setup as outputs. these should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other cmos inputs. also note that additional standby current will also be required if the confguration options have enabled the lxt or lirc oscillator. in the idle1 mode the system oscillator is on, if the system oscillator is from the high speed oscillator, the additional standby current will also be perhaps in the order of several hundred micro- amps. wake-up to minimise power consumption the device can enter the sleep or any idle mode, where the cpu will be switched off. however, when the device is woken up again, it will take a considerable time for the original system oscillator to restart, stablise and allow normal operation to resume. after the system enters the sleep or idle mode, it can be woken up from one of various sources listed as follows: ? an external falling edge on port a ? a system interrupt ? a wdt overfow if the device is woken up by a wdt overfow, a watchdog timer reset will be initiated. the pdf fag is cleared by a system power-up or executing the clear watchdog timer instructions and is set when executing the "halt" instruction. the to fag is set if a wdt time-out occurs, and causes a wake-up that only resets the program counter and stack pointer, the other fags remain in their original status. each pin on port a can be setup using the pawu register to permit a negative transition on the pin to wake up the system. when a port a pin wake-up occurs, the program will resume execution at the instruction following the "halt" instruction. if the system is woken up by an interrupt, then two possible situations may occur. the frst is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the "halt" instruction. in this situation, the interrupt which woke up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is fnally enabled or when a stack level becomes free. the other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. if an interrupt request flag is set high before entering the sleep or idle mode, the wake-up function of the related interrupt will be disabled.
rev. 1.00 48 de?e??e? 01? ?01? rev. 1.00 49 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom programming considerations the high speed and low speed oscillators both use the same sst counter. for example, if the system is woken up from the sleep0 mode and both the hirc and lxt oscillators need to start-up from an off state. the lxt oscillator uses the sst counter after hirc oscillator has finished its sst period. ? if the device is woken up from the sleep0 mode to the fast mode, the high speed system oscillator needs an sst period. the device will execute frst instruction after hto is "1". at this time, the lxt oscillator may not be stability if f sub is from lxt oscillator. the same situation occurs in the power-on state. the lxt oscillator is not ready yet when the frst instruction is executed. ? if the device is woken up from the sleep1 mode to fast mode, and the system clock source is from hxt oscillator and fsten is "1", the system clock can be switched to the lirc oscillator after wake up. ? there are peripheral functions, such as wdt and tms, for which the f sys is used. if the system clock source is switched from f h to f sub , the clock source to the peripheral functions mentioned above will change accordingly. ? the on/off condition of f sub and f s depends upon whether the wdt is enabled or disabled as the wdt clock source is selected from f s .
rev. 1.00 50 de?e??e? 01? ?01? rev. 1.00 51 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom watchdog timer the watchdog timer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. watchdog timer clock source the watchdog timer clock source is provided by the internal clock, f s , which is sourced from t he lirc or lxt osc illator. the lxt oscillator is supplied by an external 32.768khz crystal. the lirc internal oscillator has an approximate period of 32khz at a supply voltage of 5v. however, it should be noted that this specifed internal clock period can vary with v dd , temperature and process variations. the watchdog timer source clock is then subdivided by a ratio of 2 8 to 2 18 to give longer timeouts, the actual value being chosen using the ws2~ws0 bits in the wdtc register. watchdog timer control register a single register, wdtc, controls the required timeout period as well as the enable/disable and mcu software reset operation. this register controls the overall operation of the watchdog timer. ? wdtc register bit 7 6 5 4 3 2 1 0 na?e we4 we3 we? we1 we0 ws? ws1 ws0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 0 1 1 bit 7~3 : wdt function software control 10101: disable 01010: enable others: reset mcu when these bits are changed to any other values due to environmental noise the microcontroller will be reset; this reset operation will be activated after a delay time, t sreset and the wrf bit in the ctrl register will be set high. bit 2~0 : wdt time-out period selection 000: 2 8 /f s 001: 2 10 /f s 010: 2 12 /f s 011: 2 14 /f s 100: 2 15 /f s 101: 2 16 /f s 110: 2 17 /f s 111: 2 18 /f s these three bits determine the division ratio of the watchdog timer source clock, which in turn determines the time-out period. ? ctrl register bit 7 6 5 4 3 2 1 0 na?e fsyson lvrf lrf wrf r/w r/w r/w r/w r/w por 0 x 0 0 "x": unknown bit 7 : f sys control in idle mode describe elsewhere. bit 6~3 unimplemented, read as "0" bit 2 : lvr function reset fag describe elsewhere.
rev. 1.00 50 de?e??e? 01? ?01? rev. 1.00 51 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom bit 1 lrf : lvr control register software reset fag describe elsewhere. bit 0 wrf : wdt control register software reset fag 0: not occur 1: occurred this bit is set high by the wdt control register software reset and cleared to 0 by the application program. note that this bit can only be cleared to zero by the application program. the watchdog timer operates by providing a device reset when its timer overfows. this means that in the application program and during normal operation the user has to strategically clear the watchdog timer before it overfows to prevent the watchdog timer from executing a reset. this is done using the clear watchdog instructions. if the program malfunctions for whatever reason, jumps to an unknown location, or enters an endless loop, these clear instructions will not be executed in the correct manner, in which case the watchdog timer will overfow and reset the device. there are fve bits, we4~we0, in the wdtc register to offer the enable/disable control and reset control of the watchdog timer. the wdt function will be disabled when the we4~we0 bits are set to a value of 10101b while the wdt function will be enabled if the we4~we0 bits are equal to 01010b. if the we4~we0 bits are set to any other values, other than 01010b and 10101b, it will reset the device after a delay time, t sreset . after power on these bits will have a v alue of 01010b. 10101b disa?le 01010b ena?le any othe? values reset mcu wat?hdog ti?e? ena?le/disa?le cont?ol under normal program operation, a watchdog timer time-out will initialise a device reset and set the status bit to. however, if the system is in the sleep or idle mode, when a watchdog timer time-out occurs, the to bit in the status register will be set and only the program counter and stack pointer will be reset. three methods can be adopted to clear the contents of the watchdog timer. the frst is a wdt reset, which means a certain value except 01010b and 10101b written into the we4~we0 bit fled, the second is using the watchdog timer software clear instruction and the third is via a halt instruction. there is only one method of using software instruction to clear the watchdog timer. that is to use the single "clr wdt" instruction to clear the wdt. the maximum time out period is when the 2 18 division ratio is selected. as an example, with a 32khz lirc oscillator as its source clock, this will give a maximum watchdog period of around 8 second for the 2 18 division ratio, and a minimum timeout of 8ms for the 2 8 division ration. clr wdt inst?u?tion 8-stage divide? wdt p?es?ale? we4~we0 ?its wdtc registe? reset mcu lxt f sub f s /? 8 8-to-1 mux clr ws?~ws0 (f s /? 8 ~ f s /? 18 ) wdt ti?e-out (? 8 /f s ~ ? 18 /f s ) lirc m u x low speed os?illato? configu?ation option halt inst?u?tion f s wat?hdog ti?e?
rev. 1.00 5? de?e??e? 01? ?01? rev. 1.00 53 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom reset and initialisation a reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. the most important reset condition is after power is frst applied to the microcontroller. in this case, internal circuitry will ensure that the microcontroller, after a short delay, will be in a well-defined state and ready to execute the frst program instruction. after this power-on reset, certain important internal registers will be set to defned states before the program commences. one of these registers is the program counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest program memory address. another type of reset is when the watchdog timer overflows and resets the microcontroller. all types of reset operations result in different register conditions being setup. another reset exists in the form of a low voltage reset, lvr, where a full reset is implemented in situations where the power supply voltage falls below a certain threshold. reset functions there are several ways in which a microcontroller reset can occur, through events occurring internally. power-on reset the most fundamental and unavoidable reset is the one that occurs after power is frst applied to the microcontroller. as well as ensuring that the program memory begins execution from the frst memory address, a power-on reset also ensures that certain other registers are preset to known conditions. all the i/o ports and port control registers will power up in a high condition ensuring that all i/o ports will be frst set to inputs. v dd powe?-on reset sst ti?e-out t rstd power-on reset timing chart low voltage reset C lvr the microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device. the lvr function is always enabled with a specifc lvr voltage v lvr . if the supply voltage of the device drops to within a range of 0.9v~v lvr such as might occur when changing the battery, the lvr will automatically reset the device internally and the lvrf bit in the ctrl register will also be set high. for a valid lvr signal, a low supply voltage, i.e., a voltage in the range between 0.9v~v lvr must exist for a time greater than that specified by t lvr in the lvd/lvr electrical characteristics . if the low supply voltage state does not exceed this value, the lvr will ignore the low supply voltage and will not perform a reset function. the actual v lvr value can be selected by the lvs7~lvs0 bits in the lvrc register. if the lvs7~lvs0 bits are changed to some certain values by the environmental noise or software setting, the lvr will reset the device after a delay time, t sreset . when this happens, the lrf bit in the ctrl register will be set high. after power on the register will have the value of 01010101b. note that the lvr function will be automatically disabled when the device enters the sleep or idle mode. lvr inte?nal reset t rstd + t sst low voltage reset timing chart
rev. 1.00 5? de?e??e? 01? ?01? rev. 1.00 53 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom ? lvrc register bit 7 6 5 4 3 2 1 0 na?e lvs ? lvs6 lvs5 lvs4 lvs3 lvs ? lvs1 lvs0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 1 0 1 bit 7~0 lvs7~lvs0 : lvr voltage select control 01010101: 2.1v 00110011: 2.55v 10011001: 3.15v 10101010: 3.8v any other value: generates mcu reset C register is reset to por value when an actual low voltage condition occurs, as specifed by one of the four defned lvr voltage values above, an mcu reset will be generated. the reset operation will be activated after the low voltage condition keeps more than a t lvr time. in this situation the register contents will remain the same after such a reset occurs. any register value, other than the four defned lvr values above, will also result in the generation of an mcu reset. the reset operation will be activated after a delay time, t sreset . however in this situation the register contents will be reset to the por value. ? ctrl register bit 7 6 5 4 3 2 1 0 na?e fsyson lvrf lrf wrf r/w r/w r/w r/w r/w por 0 x 0 0 "x": unknown bit 7 fsyson : f c ontrol in idle mode describe elsewhere. bit 6~3 unimplemented, read as "0" bit 2 lvrf lvr function reset fag 0: not occur 1: occurred this bit is set high when a specifc low voltage reset situation condition occurs. this bit can only be cleared to zero by the application program. bit 1 lrf : lvr control register software reset fag 0: not occur 1: occurred this bit is set to 1 if the lvrc register contains any non-defned lvr voltage register values. this in effect acts like a software-reset function. this bit can only be cleared to 0 by the application program. bit 0 wrf wdt control register software reset fag describe elsewhere . watchdog time-out reset during normal operation the watchdog time-out reset during normal operation in the fast or slow mode is the same as lvr reset except that the watchdog time-out fag to will be set high. wdt ti?e-out inte?nal reset t rstd + t sst wdt time-out reset during normal operation timing chart
rev. 1.00 54 de?e??e? 01? ?01? rev. 1.00 55 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom watchdog time-out reset during sleep or idle mode the watchdog time-out reset during sleep or idle mode is a little different from other kinds of reset. most of the conditions remain unchanged except that the program counter and the stack pointer will be cleared to zero and the to fag will be set high. refer to the system start up time characteristics for t sst details. wdt ti?e-out inte?nal reset t sst wdt time-out reset during sleep or idle mode timing chart reset initial conditions the different types of reset described affect the reset fags in different ways. these fags, known as pdf and to are located in the status register and are controlled by various microcontroller operations, such as the sleep or idle mode function or watchdog timer. the reset flags are shown in the table: to pdf reset conditions 0 0 powe?-on ?eset u u lvr ?eset du? ing fast o? slow mode ope?ation 1 u wdt ti ?e-out ?eset du? ing fast o? slow mode ope?ation 1 1 wdt ti ?e-out ?eset du?ing idle o? sleep mode ope?ation "u" stands fo? un?hanged the following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. item condition after reset p?og?a? counte? reset to ze?o inte??upts all inte??upts will ?e disa?led wdt ? ti? e bases clea? afte? ?eset? wdt ?egins ?ounting ti ?e? modules ti ?e? modules will ?e tu? ned off input/output po?ts i/o po?ts will ? e setup as inputs and an0~an? as a/d input pins sta?k pointe? sta?k pointe? will point to the top of the sta?k the different kinds of resets all affect the internal registers of the microcontroller in different ways. to ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. the following table describes how each type of reset affects each of the microcontroller internal registers.
rev. 1.00 54 de?e??e? 01? ?01? rev. 1.00 55 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom register reset (power on) lvr reset (normal operation) wdt time-out (normal operation) wdt time-out (sleep or idle) iar0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu mp0 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu iar1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu mp1 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu bp ---- --0 ---- --0 ---- --0 ---- ---u acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu pcl 0000 0000 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tblh xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tbhp ---x xxxx ---u uuuu ---u uuuu ---u uuuu status --00 xxxx --uu uuuu --1u uuuu --11 uuuu smod 0000 0011 0000 0011 0000 0011 uuuu uuuu lvdc --00 0000 --00 0000 --00 0000 --uu uuuu integ ---- 0000 ---- 0000 ---- 0000 ---- uuuu intc0 -000 0000 -000 0000 -000 0000 -uuu uuuu intc1 0000 0000 0000 0000 0000 0000 uuuu uuuu intc? 0000 0000 0000 0000 0000 0000 uuuu uuuu mfi0 --00 --00 --00 --00 --00 --00 --uu --uu mfi1 0000 0000 0000 0000 0000 0000 uuuu uuuu mfi? --00 --00 --00 --00 --00 --00 --uu --uu pa 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 uuuu uuuu papu 0000 0000 0000 0000 0000 0000 uuuu uuuu pawu 0000 0000 0000 0000 0000 0000 uuuu uuuu tmpc 00-- -000 00-- -000 00-- -000 uu-- -uuu wdtc 0101 0011 0101 0011 0101 0011 uuuu uuuu tbc 0011 0111 0011 0111 0011 0111 uuuu uuuu ctrl 0--- -x00 0--- -100 0--- -000 u--- -uuu lvrc 0101 0101 0101 0101 0101 0101 uuuu uuuu eea --00 0000 --00 0000 --00 0000 --uu uuuu eed 0000 0000 0000 0000 0000 0000 uuuu uuuu sadol xxxx ---- xxxx ---- xxxx ---- uuuu ---- xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu sadoh xxxx xxxx xxxx xxxx xxxx xxxx uuuu ---- (adrfs=0) uuuu uuuu (adrfs=1) ---- xxxx ---- xxxx ---- xxxx uuuu uuuu (adrfs=0) ---- uuuu (adrfs=1) sadc0 0000 0000 0000 0000 0000 0000 uuuu uuuu sadc1 0000 0000 0000 0000 0000 0000 uuuu uuuu acerl 0000 0000 0000 0000 0000 0000 uuuu uuuu pb -111 1111 -111 1111 -111 1111 -uuu uuuu pbc -111 1111 -111 1111 -111 1111 -uuu uuuu pbpu -000 0000 -000 0000 -000 0000 -uuu uuuu ctmc0 0000 0--- 0000 0--- 0000 0--- uuuu u---
rev. 1.00 56 de?e??e? 01? ?01? rev. 1.00 5? de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom register reset (power on) lvr reset (normal operation) wdt time-out (normal operation) wdt time-out (sleep or idle) ctmc1 0000 0000 0000 0000 0000 0000 uuuu uuuu ctmdl 0000 0000 0000 0000 0000 0000 uuuu uuuu ctmdh 0000 0000 0000 0000 0000 0000 uuuu uuuu ctmal 0000 0000 0000 0000 0000 0000 uuuu uuuu ctmah 0000 0000 0000 0000 0000 0000 uuuu uuuu ctmrp 0000 0000 0000 0000 0000 0000 uuuu uuuu stmc0 0000 0--- 0000 0--- 0000 0--- uuuu u--- stmc1 0000 0000 0000 0000 0000 0000 uuuu uuuu stmdl 0000 0000 0000 0000 0000 0000 uuuu uuuu stmdh 0000 0000 0000 0000 0000 0000 uuuu uuuu stmal 0000 0000 0000 0000 0000 0000 uuuu uuuu stmah 0000 0000 0000 0000 0000 0000 uuuu uuuu stmrp 0000 0000 0000 0000 0000 0000 uuuu uuuu ptmc0 0000 0--- 0000 0--- 0000 0--- uuuu u--- ptmc1 0000 0000 0000 0000 0000 0000 uuuu uuuu ptmdl 0000 0000 0000 0000 0000 0000 uuuu uuuu ptmdh ---- --00 ---- --00 ---- --00 ---- --uu ptmal 0000 0000 0000 0000 0000 0000 uuuu uuuu ptmah ---- --00 ---- --00 ---- --00 ---- --uu ptmrpl 0000 0000 0000 0000 0000 0000 uuuu uuuu ptmrph ---- --00 ---- --00 ---- --00 ---- --uu cpc 1000 0001 1000 0001 1000 0001 uuuu uuuu pc ---- -111 ---- -111 ---- -111 ---- -uuu pcc ---- -111 ---- -111 ---- -111 ---- -uuu pcpu ---- -000 ---- -000 ---- -000 ---- -uuu simc0 111- 0000 111- 0000 111- 0000 uuu- uuuu simc1 1000 0001 1000 0001 1000 0001 uuuu uuuu simd xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu sima/simc? 0000 0000 0000 0000 0000 0000 0000 0000 simtoc 0000 0000 0000 0000 0000 0000 uuuu uuuu ifs ---- -000 ---- -000 ---- -000 ---- -uuu usr 0000 1011 0000 1011 0000 1011 uuuu uuuu ucr1 0000 00x0 0000 00x0 0000 00x0 uuuu uuuu ucr? 0000 0000 0000 0000 0000 0000 uuuu uuuu brg xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu txr_rxr xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu eec ---- 0000 ---- 0000 ---- 0000 ---- uuuu note: "u" stands for unchanged "x" stands for unknown "-" stands for unimplemented
rev. 1.00 56 de?e??e? 01? ?01? rev. 1.00 5? de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom input/output ports holtek microcontrollers offer considerable fexibility on their i/o ports. with the input or output designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an i/o structure to meet the needs of a wide range of application possibilities. the device provides bidirectional input/output lines labeled with port names pa ~ pc . these i/o ports are mapped to the ram data memory with specifc addresses as shown in the special purpose data memory table. all of these i/o ports can be used for input and output operations. for input operation, these ports are non-latching, which means the inputs must be ready at the t2 rising edge of instruction "mov a, [m]", where m denotes the port address. for output operation, all the data is latched and remains unchanged until the output latch is rewritten. the device supports source current driving capability for each i/o port. users should refer to the input/output characteristics for i/o port source current details. register name bit 7 6 5 4 3 2 1 0 pa pa ? pa6 pa5 pa4 pa3 pa ? pa1 pa0 pac pac ? pac6 pac5 pac4 pac3 pac ? pac1 pac0 papu papu ? papu6 papu5 papu4 papu3 papu ? papu1 papu0 pawu pawu ? pawu6 pawu5 pawu4 pawu3 pawu ? pawu1 pawu0 pb pb6 pb5 pb4 pb3 pb? pb1 pb0 pbc pbc6 pbc5 pbc4 pbc3 pbc? pbc1 pbc0 pbpu pbpu6 pbpu5 pbpu4 pbpu3 pbpu? pbpu1 pbpu0 pc pc? pc1 pc0 pcc pcc? pcc1 pcc0 pcpu pcpu? pcpu1 pcpu0 ifs rxctl txps rxps "": uni?ple?ented? ?ead as "0" i/o logic function register list pull-high resistors many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. to eliminate the need for these external resistors, all i/o pins, when confgured as an input have the capability of being connected to an internal pull-high resistor. these pull-high resistors are selected using register s papu~ pcpu, and are im plemented using weak pmos transistors. ? pxpu register bit 7 6 5 4 3 2 1 0 na?e pxpu? pxpu6 pxpu5 pxpu4 pxpu3 pxpu? pxpu1 pxpu0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 pxpun : i/o port x pin pull-high function control 0: disable 1: enable the pxpun bit is used to control the pin pull-high function. here the "x" can be a, b or c. however, the actual available bits for each i/o port may be different.
rev. 1.00 58 de?e??e? 01? ?01? rev. 1.00 59 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom port a wake-up the halt instruction forces the microcontroller into the sleep or idle mode which preserves power, a feature that is important for battery and other low-power applications. various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the port a pins from high to low. this function is especially suitable for applications that can be woken up via external switches. each pin on port a can be selected individually to have this wake-up feature using the pawu register. ? pawu register bit 7 6 5 4 3 2 1 0 na?e pawu ? pawu6 pawu5 pawu4 pawu3 pawu ? pawu1 pawu0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 ~0 pawu7~pawu0 : pa7~pa0 wake-up function control 0: disable 1: enable i/o port control registers each port has its own control register, known as pac~pcc, which controls the input/output configuration. with this control register, each cmos output or input can be reconfigured dynamically under software control. each pin of the i/o ports is directly mapped to a bit in its associated port control register. for the i/o pin to function as an input, the corresponding bit of the control register must be written as a "1". this will then allow the logic state of the input pin to be directly read by instructions. when the corresponding bit of the control register is written as a "0", the i/o pin will be setup as a cmos output. if the pin is currently setup as an output, instructions can still be used to read the output register. however, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. ? pxc register bit 7 6 5 4 3 2 1 0 na?e pxc? pxc5 pxc5 pxc4 pxc3 pxc? pxc1 pxc0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 pxcn : i/o port x pin type selection 0: output 1: input the pxcn bit is used to control the pin type selection. here the "x" can be a, b or c. however, the actual available bits for each i/o port may be different. pin-remapping function the fexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions, many of these difficulties can be overcome. the way in which the pin function of each pin is selected is different for each function and a priority order is established where more than one pin function is selected simultaneously. additionally there is one register, ifs, to establish certain pin functions. if the pin-shared pin function have multiple outputs simultaneously, its pin names at the right side of the "/" sign can be used for higher priority.
rev. 1.00 58 de?e??e? 01? ?01? rev. 1.00 59 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom ? ifs register bit 7 6 5 4 3 2 1 0 na?e rxctl txps rxps r/w r/w r/w r/w por 0 0 0 bit 7~3 unimplemented, read as "0" bit 2 rxctl : rx enable control 0: disable 1: enable bit 1 txps : uart tx pin-remapping selection 0: pa6 1: pb3 bit 0 rxps : uart rx pin-remapping selection 0: pa7 1: pb4 i/o pin structures the accompanying diagram illustrates the internal structures of the i/o logic function. as the exact logical construction of the i/o pin will differ from this drawing, it is supplied as a guide only to assist with the functional understanding of the logic function i/o pins. the wide range of pin-shared structures does not permit all types to be shown. m u x vdd cont?ol bit data bit data bus w?ite cont?ol registe? chip reset read cont?ol registe? read data registe? w?ite data registe? syste? wake-up wake-up sele?t i/o pin weak pull-up pull-high registe? sele?t q d ck q d ck q q s s pa only logic function input/output structure
rev. 1.00 60 de?e??e? 01? ?01? rev. 1.00 61 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom programming considerations within the user program, one of the frst things to consider is port initialisation. after a reset, all of the i/o data and port control registers will be set high. this means that all i/o pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high selections have been chosen. if the port control registers, pac~ pcc , are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data registers, pa~ pc , are frst programmed. selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the "set [m].i" and "clr [m].i" instructions. note that when using these bit control instructions, a read-modify-write operation takes place. the microcontroller must frst read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. port a has the additional capability of providing wake-up functions. when the device is in the sleep or idle mode, various methods are available to wake the device up. one of these is a high to low transition of any of the port a pins. single or multiple pins on port a can be setup to have this function.
rev. 1.00 60 de?e??e? 01? ?01? rev. 1.00 61 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom timer modules C tm one of the most fundamental functions in any microcontroller devices is the ability to control and measure time. to implement time related functions the device includes several timer modules, generally abbreviated to the name tm. the tms are multi-purpose timing units and serve to provide operations such as timer/counter, input capture, compare match output and single pulse output as well as being the functional unit for the generation of pwm signals. each of the tms has two interrupts. the addition of input and output pins for each tm ensures that users are provided with timing units with a wide and fexible range of features. the common features of the different tm types are described here with more detailed information provided in the individual compact, standard and periodic tm sections. introduction the device contains three tms and each individual tm can be categorised as a certain type, namely compact type tm, standard type tm or periodic type tm. although similar in nature, the different tm types vary in their feature complexity. the common features to all of the compact, standard and periodic type tms will be described in this section and the detailed operation regarding each of the tm types will be described in separate sections. the main features and differences between the three types of tms are summarised in the accompanying table. tm function ctm stm ptm ti ?e?/counte? input captu?e co?pa?e mat?h output pwm channels 1 1 1 single pulse output 1 1 pwm align ?ent edge edge edge pwm adjust ?ent pe?iod & duty duty o? pe?iod duty o? pe?iod duty o? pe?iod tm function summary tm operation the different types of tm offer a diverse range of functions, from simple timing operations to pwm signal generation. the key to understanding how the tm operates is to see it in terms of a free running count-up counter whose value is then compared with the value of pre-programmed internal comparators. when the free running count-up counter has the same value as the pre-programmed comparator, known as a compare match situation, a tm interrupt signal will be generated which can clear the counter and perhaps also change the condition of the tm output pin. the internal tm counter is driven by a user selectable clock source, which can be an internal clock or an external pin. tm clock source the clock source which drives the main counter in each tm can originate from various sources. the selection of the required clock source is implemented using the xtck2~xtck0 bits in the xtm control registers, where "x" stands for c, s or p type tm. the clock source can be a ratio of the system clock, f sys , or the internal high clock, f h , the f sub clock source or the external xtck pin. the xtck pin clock source is used to allow an external signal to drive the tm as an external clock source for event counting.
rev. 1.00 6? de?e??e? 01? ?01? rev. 1.00 63 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom tm interrupts the compact type, standard type and periodic type tms each have two internal interrupts, one for each of the internal comparator a or comparator p, which generate a tm interrupt when a compare match condition occurs. when a tm interrupt is generated it can be used to clear the counter and also to change the state of the tm output pin. tm external pins each of the tms, irrespective of what type, has one tm input pin with the label xtck. the xtm input pin, xtck, is essentially a clock source for the xtm and is selected using the xtck2~xtck0 bits in the xtmc0 register. this external tm input pin allows an external clock source to drive the internal tm. the xtck input pin can be chosen to have either a rising or falling active edge. the stck and ptck pins are also used as the external trigger input pin in single pulse output mode for the stm and ptm respectively. the tms each have one output pin with the label xtp. when the tm is in the compare match output mode, these pins can be controlled by the tm to switch to a high or low level or to toggle when a compare match situation occurs. the external xtp output pin is also the pin where the tm generates the pwm output waveform. the stp and ptp pins also act as an input when the tm is setup to operate in the capture input mode. as the xtp pins are pin-shared with other functions, the xtp pin function is enabled or disabled according to the internal tm on/off control, operation mode and output control settings. when the corresponding tm confguration selects the xtp pin to be used as an output pin, the associated pin will be setup as an external tm output pin. if the tm confguration selects the xtp pin to be setup as an input pin, the input signal supplied on the associated pin can be derived from an external signal and other pin-shared output function. if the tm confguration determines that the xtp pin function is not used, the associated pin will be controlled by other pin-shared functions. the details of the xtp pin for each tm type is provided in the accompanying table. ctm stm ptm input output input output input output ctck ctp stck? stp stp ptck? ptp ptp tm external pins tm input/output pin control register selecting to have a tm input/output or whether to retain its other shared function is implemented using one register with a single bit in each register corresponding to a tm input/output pin. setting the bit high will setup the corresponding pin as a tm input/output if reset to zero the pin will retain its original other functions. ctm pb3/ctp t?cp pb3 output fun?tion 0 1 pa6/ctck ctck input output 0 1 pb3 ctm function pin control block diagram
rev. 1.00 6? de?e??e? 01? ?01? rev. 1.00 63 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom stm pa0/stp t0cp pa0 output fun?tion 0 1 captu?e input pb?/stck stck input output 0 1 pa0 stm function pin control block diagram ptm pa?/ptp t1cp pa? output fun?tion 0 1 captu?e input 0 1 t1capts pa4/ptck ptck input output 0 1 pa? ptm function pin control block diagram ? tmpc register bit 7 6 5 4 3 2 1 0 na?e clop vrefs t?cp t1cp t0cp r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7 clop : clo pin control 0: disable 1: enable bit 6 vrefs : vref pin control 0: disable 1: enable bit 5~3 unimplemented, read as "0" bit 2 t2cp : ctp pin control 0: disable 1: enable bit 1 t1cp : ptp pin control 0: disable 1: enable bit 0 t0cp : stp pin control 0: disable 1: enable
rev. 1.00 64 de?e??e? 01? ?01? rev. 1.00 65 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom programming considerations the tm counter registers and the capture/compare ccra and ccrp registers, all have a low and high byte structure. the high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buffer, reading or writing to these register pairs must be carried out in a specifc way. the important point to note is that data transfer to and from the 8-bit buffer and its related low byte only takes place when a write or read operation to its corresponding high byte is executed. as the ccra and ccrp registers are implemented in the way shown in the following diagram and accessing these register pairs is carried out in a specifc way as described above, it is recommended to use the "mov" instruction to access the ccra and ccrp low byte registers, named xtmal and ptmrpl, using the following access procedures. accessing the ccra or ccrp low byte registers without following these access procedures will result in unpredictable values. data bus 8-?it buffe? xtmdh xtmdl xtmah xtmal xtm counte? registe? (read only) xtm ccra registe? (read/w?ite) ptmrph ptmrpl ptm ccrp registe? (read/w?ite) the following steps show the read and write procedures: ? writing data to ccra or ccrp ? step 1. write data to low byte xtmal or ptmrpl C note that here data is only written to the 8-bit buffer. ? step 2. write data to high byte xtmah or ptmrph C here data is written directly to the high byte registers and simultaneously data is latched from the 8-bit buffer to the low byte registers. ? reading data from the counter registers and ccra or ccrp ? step 1. read data from the high byte xtmdh, xtmah or ptmrph C here data is read directly from the high byte registers and simultaneously data is latched from the low byte register into the 8-bit buffer. ? step 2. read data from the low byte xtmdl, xtmal or ptmrpl C this step reads data from the 8-bit buffer.
rev. 1.00 64 de?e??e? 01? ?01? rev. 1.00 65 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom compact type tm C ctm although the simplest form of the three tm types, the compact type tm still contains three operating modes, which are compare match output, timer/event counter and pwm output modes. the compact type tm can also be controlled with an external input pin and can drive one external output pin. ctm core ctm input pin ctm output pin 16-?it ctm ctck ctp f sys f sys /4 f h /64 f h /16 f sub f sub ctck 000 001 010 011 100 101 110 111 ctck?~ctck0 16-?it count-up counte? 8-?it co?pa?ato? p ccrp ?8~?15 ?0~?15 16-?it co?pa?ato? a cton ctpau co?pa?ato? a mat?h co?pa?ato? p mat?h counte? clea? 0 1 output cont?ol pola?ity cont?ol ctp ctoc ctm1? ctm0 ctio1? ctio0 ctmaf inte??upt ctmpf inte??upt ctpol ccra ctcclr compact type tm block diagram compact type tm operation at its core is a 16-bit count-up counter which is driven by a user selectable internal or external clock source. there are also two internal comparators with the names, comparator a and comparator p. these comparators will compare the value in the counter with ccrp and ccra registers. the ccrp is 8-bit wide whose value is compared with the highest eight bits in the counter while the ccra is 16-bit wide and therefore compares with all counter bits. the only way of changing the value of the 16-bit counter using the application program, is to clear the counter by changing the cton bit from low to high. the counter will also be cleared automatically by a counter overfow or a compare match with one of its associated comparators. when these conditions occur, a ctm interrupt signal will also usually be generated. the compact type tm can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control an output pin. all operating setup conditions are selected using relevant internal registers. compact type tm register description overall operation of the compact tm is controlled using a series of registers. a read only register pair exists to store the internal counter 16-bit value, while a read/write register pair exists to store the internal 16-bit ccra value. the ctmrp register is used to store the 8-bit ccrp value. the remaining two registers are control registers which setup the different operating and control modes. register name bit 7 6 5 4 3 2 1 0 ctmc0 ctpau ctck? ctck1 ctck0 cton ctmc1 ctm1 ctm0 ctio1 ctio0 ctoc ctpol ctdpx ctcclr ctmdl d? d6 d5 d4 d3 d? d1 d0 ctmdh d15 d14 d13 d1? d11 d10 d9 d8 ctmal d? d6 d5 d4 d3 d? d1 d0 ctmah d15 d14 d13 d1? d11 d10 d9 d8 ctmrp ctrp? ctrp6 ctrp5 ctrp4 ctrp3 ctrp? ctrp1 ctrp0 16-bit compact tm register list
rev. 1.00 66 de?e??e? 01? ?01? rev. 1.00 6? de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom ? ctmc0 register bit 7 6 5 4 3 2 1 0 na?e ctpau ctck? ctck1 ctck0 cton r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7 ctpau : ctm counter pause control 0: run 1: pause the counter can be paused by setting this bit high. clearing the bit to zero restores normal counter operation. when in a pause condition the ctm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 ctck2~ctck0 : select ctm counter clock 000: f /4 001: f 010: f /16 011: f /64 100: f 101: f 110: ctck rising edge clock 111: ctck falling edge clock these three bits are used to select the clock source for the ctm. the external pin clock source can be chosen to be active on the rising or falling edge. the clock source is the system clock, while f and f are other internal clocks, the details of which can be found in the oscillator section. bit 3 cton : ctm counter on/off control 0: off 1: on this bit controls the overall on/off function of the ctm. setting the bit high enables the counter to run while clearing the bit disables the ctm. clearing this bit to zero will stop the counter from counting and turn off the ctm which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. if the ctm is in the compare match output mode or the pwm output mode then the ctm output pin will be reset to its initial condition, as specifed by the ctoc bit, when the cton bit changes from low to high. bit 2~0 unimplemented, read as "0" ? ctmc1 register bit 7 6 5 4 3 2 1 0 na?e ctm1 ctm0 ctio1 ctio0 ctoc ctpol ctdpx ctcclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 ctm1~ctm0 : select ctm operating mode 00: compare match output mode 01: undefned 10: pwm output mode 11: timer/counter mode these bits setup the required operating mode for the ctm. to ensure reliable operation the ctm should be switched off before any changes are made to the ctm1 and ctm0 bits. in the timer/counter mode, the ctm output pin control must be disabled.
rev. 1.00 66 de?e??e? 01? ?01? rev. 1.00 6? de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom bit 5~4 ctio1~ctio0 : select ctm function compare match output mode 00: no change 01: output low 10: output high 11: toggle output pwm output mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: undefned timer/counter mode unused these two bits are used to determine how the ctm output pin changes state when a certain condition is reached. the function that these bits select depends upon in which mode the ctm is running. in the compare match output mode, the ctio1 and ctio0 bits determine how the ctm output pin changes state when a compare match occurs from the comparator a. the ctm output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the ctm output pin should be setup using the ctoc bit in the ctmc1 register. note that the output level requested by the ctio1 and ctio0 bits must be different from the initial value setup using the ctoc bit otherwise no change will occur on the ctm output pin when a compare match occurs. after the ctm output pin changes state, it can be reset to its initial level by changing the level of the cton bit from low to high. in the pwm output mode, the ctio1 and ctio0 bits determine how the ctm output pin changes state when a certain compare match condition occurs. the pwm output function is modifed by changing these two bits. it is necessary to only change the values of the ctio1 and ctio0 bits only after the ctm has been switched off. unpredictable pwm outputs will occur if the ctio1 and ctio0 bits are changed when the ctm is running. bit 3 ctoc : ctp output control compare match output mode 0: initial low 1: initial high pwm output mode 0: active low 1: active high this is the output control bit for the ctm output pin. its operation depends upon whether ctm is being used in the compare match output mode or in the pwm output mode. it has no effect if the ctm is in the timer/counter mode. in the compare match output mode it determines the logic level of the ctm output pin before a compare match occurs. in the pwm output mode it determines if the pwm signal is active high or active low. bit 2 ctpol : ctp output polarity control 0: non-invert 1: invert this bit controls the polarity of the ctp output pin. when the bit is set high the ctm output pin will be inverted and not inverted when the bit is zero. it has no effect if the tm is in the timer/counter mode. bit 1 ctdpx : ctm pwm duty/period control 0: ccrp C period; ccra C duty 1: ccrp C duty; ccra C period this bit determines which of the ccra and ccrp registers are used for period and duty control of the pwm waveform.
rev. 1.00 68 de?e??e? 01? ?01? rev. 1.00 69 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom bit 0 ctcclr : ctm counter clear condition selection 0: ctm comparator p match 1: ctm comparator a match this bit is used to select the method which clears the counter. remember that the compact tm contains two comparators, comparator a and comparator p, either of which can be selected to clear the internal counter. with the ctcclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low, the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow. a counter overfow clearing method can only be implemented if the ccrp bits are all cleared to zero. the ctcclr bit is not used in the pwm output mode. ? ctmdl register bit 7 6 5 4 3 2 1 0 na?e d? d6 d5 d4 d3 d? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 d7~d0 : ctm counter low byte register bit 7~bit 0 ctm 16-bit counter bit 7~bit 0 ? ctmdh register bit 7 6 5 4 3 2 1 0 na?e d15 d14 d13 d1? d11 d10 d9 d8 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 d15~d8 : ctm counter high byte register bit 7~bit 0 ctm 16-bit counter bit 15~bit 8 ? ctmal register bit 7 6 5 4 3 2 1 0 na?e d? d6 d5 d4 d3 d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 d7~d0 : ctm ccra low byte register bit 7~bit 0 ctm 16-bit ccra bit 7~bit 0 ? ctmah register bit 7 6 5 4 3 2 1 0 na?e d15 d14 d13 d1? d11 d10 d9 d8 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 d15~d8 : ctm ccra high byte register bit 7~bit 0 ctm 16-bit ccra bit 15~bit 8
rev. 1.00 68 de?e??e? 01? ?01? rev. 1.00 69 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom ? ctmrp register bit 7 6 5 4 3 2 1 0 na?e ctrp? ctrp6 ctrp5 ctrp4 ctrp3 ctrp? ctrp1 ctrp0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 ctrp7~ctrp0 : ctm ccrp 8-bit register, compared with the ctm counter bit 15~bit 8 comparator p match period= 0: 65536 ctm clocks 1~255: 256 (1~255) ctm clocks these eight bits are used to setup the value on the internal ccrp 8-bit register, which are then compared with the internal counters highest eight bits. the result of this comparison can be selected to clear the internal counter if the ctcclr bit is set to zero. setting the ctcclr bit to zero ensures that a compare match with the ccrp values will reset the internal counter. as the ccrp bits are only compared with the highest eight counter bits, the compare values exist in 256 clock cycle multiples. clearing all eight bits to zero is in effect allowing the counter to overflow at its maximum value. compact type tm operating modes the compact type tm can operate in one of three operating modes, compare match output mode, pwm output mode or timer/counter mode. the operating mode is selected using the ctm1 and ctm0 bits in the ctmc1 register. compare match output mode to select this mode, bits ctm1 and ctm0 in the ctmc1 register, should be set to "00" respectively. in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overfow, a compare match from comparator a and a compare match from comparator p. when the ctcclr bit is low, there are two ways in which the counter can be cleared. one is when a compare match occurs from comparator p, the other is when the ccrp bits are all zero which allows the counter to overfow. here both ctmaf and ctmpf interrupt request fags for the comparator a and comparator p respectively, will both be generated. if the ctcclr bit in the ctmc1 register is high then the counter will be cleared when a compare match occurs from comparator a. however, here only the ctmaf interrupt request fag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when ctcclr is high no ctmpf interrupt request fag will be generated. if the ccra bits are all zero, the counter will overfow when its reaches its maximum 16-bit, ffff hex, value, however here the ctmaf interrupt request fag will not be generated. as the name of the mode suggests, after a comparison is made, the ctm output pin will change state. the ctm output pin condition however only changes state when a ctmaf interrupt request fag is generated after a compare match occurs from comparator a. the ctmpf interrupt request fag, generated from a compare match occurs from comparator p, will have no effect on the ctm output pin. the way in which the ctm output pin changes state are determined by the condition of the ctio1 and ctio0 bits in the ctmc1 register. the ctm output pin can be selected using the ctio1 and ctio0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from comparator a. the initial condition of the ctm output pin, which is setup after the cton bit changes from low to high, is setup using the ctoc bit. note that if the ctio1 and ctio0 bits are zero then no pin change will take place.
rev. 1.00 ?0 de?e??e? 01? ?01? rev. 1.00 ?1 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom counte? value 0xffff ccrp ccra cton ctpau ctpol ccrp int. flag ctmpf ccra int. flag ctmaf ctm o/p pin ti?e ccrp=0 ccrp > 0 counte? ove?flow ccrp > 0 counte? ?lea?ed ?y ccrp value pause resu?e stop counte? resta?t ctcclr = 0; ctm [1:0] = 00 output pin set to initial level low if ctoc=0 output toggle with ctmaf flag note ctio [1:0] = 10 a?tive high output sele?t he?e ctio [1:0] = 11 toggle output sele?t output not affe?ted ?y ctmaf flag. re?ains high until ?eset ?y cton ?it output pin reset to initial value output ?ont?olled ?y othe? pin-sha?ed fun?tion output inve?ts when ctpol is high compare match output mode C ctcclr = 0 notes: 1. with ctcclr = 0, a comparator p match will clear the counter 2. the ctm output pin is controlled only by the ctmaf fag 3. the output pin is reset to its initial state by a cton bit rising edge
rev. 1.00 ?0 de?e??e? 01? ?01? rev. 1.00 ?1 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom counte? value 0xffff ccrp ccra cton ctpau ctpol ctm o/p pin ti?e ccra=0 ccra = 0 counte? ove?flow ccra > 0 counte? ?lea?ed ?y ccra value pause resu?e stop counte? resta?t output pin set to initial level low if ctoc=0 output toggle with ctmaf flag note ctio [1:0] = 10 a?tive high output sele?t he?e ctio [1:0] = 11 toggle output sele?t output not affe?ted ?y ctmaf flag. re?ains high until ?eset ?y cton ?it output pin reset to initial value output ?ont?olled ?y othe? pin-sha?ed fun?tion output inve?ts when ctpol is high ctmpf not gene?ated no ctmaf flag gene?ated on ccra ove?flow output does not ?hange ctcclr = 1; ctm [1:0] = 00 ccra int. flag ctmaf ccrp int. flag ctmpf compare match output mode C ctcclr = 1 notes: 1. with ctcclr = 1, a comparator a match will clear the counter 2. the ctm output pin is controlled only by the ctmaf fag 3. the output pin is reset to its initial state by a cton bit rising edge 4. the ctmpf fag is not generated when ctcclr = 1
rev. 1.00 ?? de?e??e? 01? ?01? rev. 1.00 ?3 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom timer/counter mode to select this mode, bits ctm1 and ctm0 in the ctmc1 register should be set to 11 respectively. the timer/counter mode operates in an identical way to the compare match output mode generating the same interrupt flags. the exception is that in the timer/counter mode the ctm output pin is not used. therefore the above description and timing diagrams for the compare match output mode can be used to understand its function. as the ctm output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared functions. pwm output mode to select this mode, bits ctm1 and ctm0 in the ctmc1 register should be set to 10 respectively. the pwm function within the ctm is useful for applications which require functions such as motor control, heating control, illumination control etc. by providing a signal of fxed frequency but of varying duty cycle on the ctm output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform is extremely fexible. in the pwm output mode, the ctcclr bit has no effect on the pwm operation. both of the ccra and ccrp registers are used to generate the pwm waveform, one register is used to clear the internal counter and thus control the pwm waveform frequency, while the other one is used to control the duty cycle. which register is used to control either frequency or duty cycle is determined using the ctdpx bit in the ctmc1 register. the pwm waveform frequency and duty cycle can therefore be controlled by the values in the ccra and ccrp registers. an interrupt fag, one for each of the ccra and ccrp, will be generated when a compare match occurs from either comparator a or comparator p. the ctoc bit in the ctmc1 register is used to select the required polarity of the pwm waveform while the two ctio1 and ctio0 bits are used to enable the pwm output or to force the tm output pin to a fxed high or low level. the ctpol bit is used to reverse the polarity of the pwm output waveform. ? 16-bit ctm, pwm output mode, edge-aligned mode, ctdpx = 0 ccrp 1~255 0 pe?iod ccrp?56 65536 duty ccra if f sys =16mhz, ctm clock source select f sys /4, ccrp=2 and ccra=128, the ctm pwm output frequency=(f sys /4)/(2 256)=f sys /2048=7.8125khz, duty=128/(2 256)=25%. if the duty value defned by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%. ? 16-bit ctm, pwm output mode, edge-aligned mode, ctdpx = 1 ccrp 1~255 0 pe?iod ccra duty ccrp?56 65536 the pwm output period is determined by the ccra register value together with the ctm clock while the pwm duty cycle is defned by the ccrp register value except when the ccrp value is equal to 0.
rev. 1.00 ?? de?e??e? 01? ?01? rev. 1.00 ?3 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom counte? value ccrp ccra cton ctpau ctpol ctm o/p pin (ctoc=1) ti?e counte? ?lea?ed ?y ccrp pause resu?e counte? stop if cton ?it low counte? reset when cton ?etu?ns high pwm duty cy?le set ?y ccra pwm ?esu?es ope?ation output ?ont?olled ?y othe? pin-sha?ed fun?tion output inve?ts when ctpol = 1 pwm pe?iod set ?y ccrp ctm o/p pin (ctoc=0) ccra int. flag ctmaf ccrp int. flag ctmpf ctdpx = 0; ctm [1:0] = 10 pwm output mode C ctdpx = 0 notes: 1. here ctdpx = 0 C counter cleared by ccrp 2. a counter clear sets the pwm period 3. the internal pwm function continues even when ctio [1:0] = 00 or 01 4. the ctcclr bit has no infuence on pwm operation
rev. 1.00 ?4 de?e??e? 01? ?01? rev. 1.00 ?5 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom counte? value ccrp ccra cton ctpau ctpol ccrp int. flag ctmpf ccra int. flag ctmaf ctm o/p pin (ctoc=1) ti?e counte? ?lea?ed ?y ccra pause resu?e counte? stop if cton ?it low counte? reset when cton ?etu?ns high pwm duty cy?le set ?y ccrp pwm ?esu?es ope?ation output ?ont?olled ?y othe? pin-sha?ed fun?tion output inve?ts when ctpol = 1 pwm pe?iod set ?y ccra ctm o/p pin (ctoc=0) ctdpx = 1; ctm [1:0] = 10 pwm output mode C ctdpx = 1 notes: 1. here ctdpx = 1 C counter cleared by ccra 2. a counter clear sets the pwm period 3. the internal pwm function continues even when ctio [1:0] = 00 or 01 4. the ctcclr bit has no infuence on pwm operation
rev. 1.00 ?4 de?e??e? 01? ?01? rev. 1.00 ?5 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom standard type tm C stm the standard type tm contains fve operating modes, which are compare match output, timer/ event counter, capture input, single pulse output and pwm output modes. the standard type tm can also be controlled with two external input pin and can drive one external output pin. stm core stm input pin stm output pin 16-?it stm stck? stp stp f sys f sys /4 f h /64 f h /16 f sub stck 000 001 010 011 100 101 110 111 stck?~stck0 16-?it count-up counte? 8-?it co?pa?ato? p ccrp ?8~?15 ?0~?15 16-?it co?pa?ato? a ston stpau co?pa?ato? a mat?h co?pa?ato? p mat?h counte? clea? 0 1 output cont?ol pola?ity cont?ol stp stoc stm1? stm0 stio1? stio0 stmaf inte??upt stmpf inte??upt stpol ccra stcclr edge dete?to? stio1? stio0 f sub stp pin input/output standard type tm block diagram standard type tm operation the size of standard type tm is 16-bit wide and its core is a 16-bit count-up counter which is driven by a user selectable internal or external clock source. there are also two internal comparators with the names, comparator a and comparator p. these comparators will compare the value in the counter with ccrp and ccra registers. the ccrp comparator is 8-bit wide whose value is compared the with highest 8 bits in the counter while the ccra is the sixteen bits and therefore compares all counter bits. the only way of changing the value of the 16-bit counter using the application program, is to clear the counter by changing the ston bit from low to high. the counter will also be cleared automatically by a counter overfow or a compare match with one of its associated comparators. when these conditions occur, a stm interrupt signal will also usually be generated. the standard type tm can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control an output pin. all operating setup conditions are selected using relevant internal registers. standard type tm register description overall operation of the standard type tm is controlled using a series of registers. a read only register pair exists to store the internal counter 16-bit value, while a read/write register pair exists to store the internal 16-bit ccra value. the stmrp register is used to store the 8-bit ccrp value. the remaining two registers are control registers which setup the different operating and control modes.
rev. 1.00 ?6 de?e??e? 01? ?01? rev. 1.00 ?? de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom register name bit 7 6 5 4 3 2 1 0 stmc0 stpau stck? stck1 stck0 ston stmc1 stm1 stm0 stio1 stio0 stoc stpol stdpx stcclr stmdl d? d6 d5 d4 d3 d? d1 d0 stmdh d15 d14 d13 d1? d11 d10 d9 d8 stmal d? d6 d5 d4 d3 d? d1 d0 stmah d15 d14 d13 d1? d11 d10 d9 d8 stmrp strp? strp6 strp5 strp4 strp3 strp? strp1 strp0 16-bit standard type tm register list ? stmc0 register bit 7 6 5 4 3 2 1 0 na?e stpau stck? stck1 stck0 ston r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7 stpau : stm counter pause control 0: run 1: pause the counter can be paused by setting this bit high. clearing the bit to zero restores normal counter operation. when in a pause condition the stm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 stck2~stck0 : select stm counter clock 000: f /4 001: f 010: f /16 011: f /64 100: f 101: f 110: stck rising edge clock 111: stck falling edge clock these three bits are used to select the clock source for the stm. the external pin clock source can be chosen to be active on the rising or falling edge. the clock source f is the system clock, while f and f are other internal clocks, the details of which can be found in the oscillator section. bit 3 ston : stm counter on/off control 0: off 1: on this bit controls the overall on/off function of the stm. setting the bit high enables the counter to run while clearing the bit disables the stm. clearing this bit to zero will stop the counter from counting and turn off the stm which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. if the stm is in the compare match output mode or pwm output mode or single pulse output mode, then the stm output pin will be reset to its initial condition, as specifed by the stoc bit, when the ston bit changes from low to high. bit 2~0 unimplemented, read as "0"
rev. 1.00 ?6 de?e??e? 01? ?01? rev. 1.00 ?? de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom ? stmc1 register bit 7 6 5 4 3 2 1 0 na?e stm1 stm0 stio1 stio0 stoc stpol stdpx stcclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 stm1~stm0 : select stm operating mode 00: compare match output mode 01: capture input mode 10: pwm output mode or single pulse output mode 11: timer/counter mode these bits setup the required operating mode for the stm. to ensure reliable operation the stm should be switched off before any changes are made to the stm1 and stm0 bits. in the timer/counter mode, the stm output pin control must be disabled. bit 5~4 stio1~stio0 : select stp external pin function compare match output mode 00: no change 01: output low 10: output high 11: toggle output pwm output mode/single pulse output mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: single pulse output capture input mode 00: input capture at rising edge of stp 01: input capture at falling edge of stp 10: input capture at rising/falling edge of stp 11: input capture disabled timer/counter mode unused these two bits are used to determine how the stm output pin changes state when a certain condition is reached. the function that these bits select depends upon in which mode the stm is running. in the compare match output mode, the stio1 and stio0 bits determine how the stm output pin changes state when a compare match occurs from the comparator a. the tm output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the stm output pin should be setup using the stoc bit in the stmc1 register. note that the output level requested by the stio1 and stio0 bits must be different from the initial value setup using the stoc bit otherwise no change will occur on the stm output pin when a compare match occurs. after the stm output pin changes state, it can be reset to its initial level by changing the level of the ston bit from low to high. in the pwm output mode, the stio1 and stio0 bits determine how the stm output pin changes state when a certain compare match condition occurs. the pwm output function is modifed by changing these two bits. it is necessary to only change the values of the stio1 and stio0 bits only after the stm has been switched off. unpredictable pwm outputs will occur if the stio1 and stio0 bits are changed when the stm is running.
rev. 1.00 ?8 de?e??e? 01? ?01? rev. 1.00 ?9 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom bit 3 stoc : stm stp output control compare match output mode 0: initial low 1: initial high pwm output mode/single pulse output mode 0: active low 1: active high this is the output control bit for the stm output pin. its operation depends upon whether stm is being used in the compare match output mode or in the pwm output mode/single pulse output mode. it has no effect if the stm is in the timer/ counter mode. in the compare match output mode it determines the logic level of the stm output pin before a compare match occurs. in the pwm output mode it determines if the pwm signal is active high or active low. in the single pulse output mode it determines the logic level of the stm output pin when the ston bit changes from low to high. bit 2 stpol : stm stp output polarity control 0: non-invert 1: invert this bit controls the polarity of the stp output pin. when the bit is set high the stm output pin will be inverted and not inverted when the bit is zero. it has no effect if the stm is in the timer/counter mode. bit 1 stdpx : stm pwm duty/period control 0: ccrp C period; ccra C duty 1: ccrp C duty; ccra C period this bit determines which of the ccra and ccrp registers are used for period and duty control of the pwm waveform. bit 0 stcclr : stm counter clear condition selection 0: comparator p match 1: comparator a match this bit is used to select the method which clears the counter. remember that the standard type tm contains two comparators, comparator a and comparator p, either of which can be selected to clear the internal counter. with the stcclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low, the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow. a counter overfow clearing method can only be implemented if the ccrp bits are all cleared to zero. the stcclr bit is not used in the pwm output mode, single pulse output mode or capture input mode. ? stmdl register bit 7 6 5 4 3 2 1 0 na?e d? d6 d5 d4 d3 d? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 d7~d0 : stm counter low byte register bit 7~bit 0 stm 16-bit counter bit 7~bit 0 ? stmdh register bit 7 6 5 4 3 2 1 0 na?e d15 d14 d13 d1? d11 d10 d9 d8 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 d15~d8 : stm counter high byte register bit 7~bit 0 stm 16-bit counter bit 15~bit 8
rev. 1.00 ?8 de?e??e? 01? ?01? rev. 1.00 ?9 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom ? stmal register bit 7 6 5 4 3 2 1 0 na?e d? d6 d5 d4 d3 d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 d7~d0 : stm ccra low byte register bit 7~bit 0 stm 16-bit ccra bit 7~bit 0 ? stmah register bit 7 6 5 4 3 2 1 0 na?e d15 d14 d13 d1? d11 d10 d9 d8 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 d15~d8 : stm ccra high byte register bit 7~bit 0 stm 16-bit ccra bit 15~bit 8 ? stmrp register bit 7 6 5 4 3 2 1 0 na?e strp? strp6 strp5 strp4 strp3 strp? strp1 strp0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 strp7~strp0 : stm ccrp 8-bit register, compared with the stm counter bit 15~bit 8 comparator p match period= 0: 65536 stm clocks 1~255: (1~255) 256 stm clocks these eight bits are used to setup the value on the internal ccrp 8-bit register, which are then compared with the internal counters highest eight bits. the result of this comparison can be selected to clear the internal counter if the stcclr bit is set to zero. setting the stcclr bit to zero ensures that a compare match with the ccrp values will reset the internal counter. as the ccrp bits are only compared with the highest eight counter bits, the compare values exist in 256 clock cycle multiples. clearing all eight bits to zero is in effect allowing the counter to overflow at its maximum value. standard type tm operation modes the standard type tm can operate in one of fve operating modes, compare match output mode, pwm output mode, single pulse output mode, capture input mode or timer/counter mode. the operating mode is selected using the stm1 and stm0 bits in the stmc1 register. compare match output mode to select this mode, bits stm1 and stm0 in the stmc1 register, should be set to 00 respectively. in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overfow, a compare match from comparator a and a compare match from comparator p. when the stcclr bit is low, there are two ways in which the counter can be cleared. one is when a compare match from comparator p, the other is when the ccrp bits are all zero which allows the counter to overfow. here both stmaf and stmpf interrupt request fags for comparator a and comparator p respectively, will both be generated. if the stcclr bit in the stmc1 register is high then the counter will be cleared when a compare match occurs from comparator a. however, here only the stmaf interrupt request fag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when stcclr is high no stmpf interrupt request fag will be generated. in the compare match output mode, the ccra can not be set to "0".
rev. 1.00 80 de?e??e? 01? ?01? rev. 1.00 81 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom if the ccra bits are all zero, the counter will overfow when its reaches its maximum 16-bit, ffff hex, value, however here the stmaf interrupt request fag will not be generated. as the name of the mode suggests, after a comparison is made, the stm output pin, will change state. the stm output pin condition however only changes state when a stmaf interrupt request fag is generated after a compare match occurs from comparator a. the stmpf interrupt request fag, generated from a compare match occurs from comparator p, will have no effect on the stm output pin. the way in which the stm output pin changes state are determined by the condition of the stio1 and stio0 bits in the stmc1 register. the stm output pin can be selected using the stio1 and stio0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from comparator a. the initial condition of the stm output pin, which is setup after the ston bit changes from low to high, is setup using the stoc bit. note that if the stio1 and stio0 bits are zero then no pin change will take place. counte? value 0xffff ccrp ccra ston stpau stpol ccrp int. flag stmpf ccra int. flag stmaf stm o/p pin ti?e ccrp=0 ccrp > 0 counte? ove?flow ccrp > 0 counte? ?lea?ed ?y ccrp value pause resu?e stop counte? resta?t stcclr = 0; stm [1:0] = 00 output pin set to initial level low if stoc=0 output toggle with stmaf flag note stio [1:0] = 10 a?tive high output sele?t he?e stio [1:0] = 11 toggle output sele?t output not affe?ted ?y stmaf flag. re?ains high until ?eset ?y ston ?it output pin reset to initial value output ?ont?olled ?y othe? pin-sha?ed fun?tion output inve?ts when stpol is high compare match output mode C stcclr = 0 notes: 1. with stcclr = 0, a comparator p match will clear the counter 2. the stm output pin is controlled only by the stmaf fag 3. the output pin is reset to its initial state by a ston bit rising edge
rev. 1.00 80 de?e??e? 01? ?01? rev. 1.00 81 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom counte? value 0xffff ccrp ccra ston stpau stpol ccrp int. flag stmpf ccra int. flag stmaf stm o/p pin ti?e ccra=0 ccra = 0 counte? ove?flow ccra > 0 counte? ?lea ?ed ?y ccra value pause resu?e stop counte? resta?t stcclr = 1; stm [1:0] = 00 output pin set to initial level low if stoc=0 output toggle with stmaf flag note stio [1:0] = 10 a?tive high output sele?t he?e stio [1:0] = 11 toggle output sele?t output not affe?ted ?y stmaf flag. re?ains high until ?eset ?y ston ?it output pin reset to initial value output ?ont?olled ?y othe? pin-sha?ed fun?tion output inve?ts when stpol is high stmpf not gene?ated no stmaf flag gene?ated on ccra ove?flow output does not ?hange compare match output mode C stcclr = 1 notes: 1. with stcclr = 1, a comparator a match will clear the counter 2. the stm output pin is controlled only by the stmaf fag 3. the output pin is reset to its initial state by a ston bit rising edge 4. the stmpf fag is not generated when stcclr = 1
rev. 1.00 8? de?e??e? 01? ?01? rev. 1.00 83 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom timer/counter mode to select this mode, bits stm1 and stm0 in the stmc1 register should be set to 11 respectively. the timer/counter mode operates in an identical way to the compare match output mode generating the same interrupt flags. the exception is that in the timer/counter mode the stm output pin is not used. therefore the above description and timing diagrams for the compare match output mode can be used to understand its function. as the stm output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared functions. pwm output mode to select this mode, bits stm1 and stm0 in the stmc1 register should be set to 10 respectively and also the stio1 and stio0 bits should be set to 10 respectively. the pwm function within the stm is useful for applications which require functions such as motor control, heating control, illumination control etc. by providing a signal of fxed frequency but of varying duty cycle on the stm output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform is extremely fexible. in the pwm output mode, the stcclr bit has no effect as the pwm period. both of the ccra and ccrp registers are used to generate the pwm waveform, one register is used to clear the internal counter and thus control the pwm waveform frequency, while the other one is used to control the duty cycle. which register is used to control either frequency or duty cycle is determined using the stdpx bit in the stmc1 register. the pwm waveform frequency and duty cycle can therefore be controlled by the values in the ccra and ccrp registers. an interrupt fag, one for each of the ccra and ccrp, will be generated when a compare match occurs from either comparator a or comparator p. the stoc bit in the stmc1 register is used to select the required polarity of the pwm waveform while the two stio1 and stio0 bits are used to enable the pwm output or to force the stm output pin to a fxed high or low level. the stpol bit is used to reverse the polarity of the pwm output waveform. ? 16-bit stm, pwm output mode, edge-aligned mode, stdpx=0 ccrp 1~255 0 pe?iod ccrp ?56 65536 duty ccra if f sys =16mhz, stm clock source is f sys /4, ccrp=2 and ccra=128, the stm pwm output frequency=(f sys /4)/(2 256)=f sys /2048=7.8125 khz, duty=128/(2 256)=25%. if the duty value defned by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%. ? 16-bit stm, pwm output mode, edge-aligned mode, stdpx=1 ccrp 1~255 0 pe?iod ccra duty ccrp ?56 65536 the pwm output period is determined by the ccra register value together with the tm clock while the pwm duty cycle is defned by the ccrp register value except when the ccrp value is equal to 0.
rev. 1.00 8? de?e??e? 01? ?01? rev. 1.00 83 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom counte? value ccrp ccra ston stpau stpol ccrp int. flag stmpf ccra int. flag stmaf stm o/p pin (stoc=1) ti?e counte? ?lea?ed ?y ccrp pause resu?e counte? stop if ston ?it low counte? reset when ston ?etu?ns high stdpx = 0; stm [1:0] = 10 pwm duty cy?le set ?y ccra pwm ?esu?es ope?ation output ?ont?olled ?y othe? pin-sha?ed fun?tion output inve?ts when stpol = 1 pwm pe?iod set ?y ccrp stm o/p pin (stoc=0) pwm output mode C stdpx = 0 notes: 1. here stdpx = 0 C counter cleared by ccrp 2. a counter clear sets the pwm period 3. the internal pwm function continues even when stio [1:0] = 00 or 01 4. the stcclr bit has no infuence on pwm operation
rev. 1.00 84 de?e??e? 01? ?01? rev. 1.00 85 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom counte? value ccrp ccra ston stpau stpol ccrp int. flag stmpf ccra int. flag stmaf stm o/p pin (stoc=1) ti?e counte? ?lea?ed ?y ccra pause resu?e counte? stop if ston ?it low counte? reset when ston ?etu?ns high stdpx = 1; stm [1:0] = 10 pwm duty cy?le set ?y ccrp pwm ?esu?es ope?ation output ?ont?olled ?y othe? pin-sha?ed fun?tion output inve?ts when stpol = 1 pwm pe?iod set ?y ccra stm o/p pin (stoc=0) pwm output mode C stdpx = 1 notes: 1. here stdpx = 1 C counter cleared by ccra 2. a counter clear sets the pwm period 3. the internal pwm function continues even when stio [1:0] = 00 or 01 4. the stcclr bit has no infuence on pwm operation
rev. 1.00 84 de?e??e? 01? ?01? rev. 1.00 85 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom single pulse output mode to select this mode, bits stm1 and stm0 in the stmc1 register should be set to 10 respectively and also the stio1 and stio0 bits should be set to 11 respectively. the single pulse output mode, as the name suggests, will generate a single shot pulse on the stm output pin. the trigger for the pulse output leading edge is a low to high transition of the ston bit, which can be implemented using the application program. however in the single pulse output mode, the ston bit can also be made to automatically change from low to high using the external stck pin, which will in turn initiate the single pulse output. when the ston bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. the ston bit should remain high when the pulse is in its active state. the generated pulse trailing edge will be generated when the ston bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from comparator a. however a compare match from comparator a will also automatically clear the ston bit and thus generate the single pulse output trailing edge. in this way the ccra value can be used to control the pulse width. a compare match from comparator a will also generate a stm interrupt. the counter can only be reset back to zero when the ston bit changes from low to high when the counter restarts. in the single pulse output mode ccrp is not used. the stcclr and stdpx bits are not used in this mode. ston ?it 0 1 s/w co??and set ston o? stck pin t?ansition ston ?it 1 0 ccra t?ailing edge s/w co??and clr ston o? ccra co?pa?e mat?h stp output pin pulse width = ccra value ccra leading edge single pulse generation
rev. 1.00 86 de?e??e? 01? ?01? rev. 1.00 8? de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom counte? value ccrp ccra ston stpau stpol ccrp int. flag stmpf ccra int. flag stmaf stm o/p pin (stoc=1) ti?e counte? stopped ?y ccra pause resu?e counte? stops ?y softwa?e counte? reset when ston ?etu?ns high stm [1:0] = 10 ; stio [1:0] = 11 pulse width set ?y ccra output inve?ts when stpol = 1 no ccrp inte??upts gene?ated stm o/p pin (stoc=0) stck pin softwa?e t?igge? clea?ed ?y ccra ?at?h stck pin t?igge? auto. set ?y stck pin softwa?e t?igge? softwa?e clea? softwa?e t?igge? softwa?e t?igge? single pulse output mode notes: 1. counter stopped by ccra 2. ccrp is not used 3. the pulse triggered by the stck pin or by setting the ston bit high 4. a stck pin active edge will automatically set the ston bit high 5. in the single pulse output mode, stio [1:0] must be set to "11" and can not be changed
rev. 1.00 86 de?e??e? 01? ?01? rev. 1.00 8? de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom capture input mode to select this mode bits stm1 and stm0 in the stmc1 register should be set to 01 respectively. this mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. the external signal is supplied on the stp pin, whose active edge can be a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the stio1 and stio0 bits in the stmc1 register. the counter is started when the ston bit changes from low to high which is initiated using the application program. when the required edge transition appears on the stp pin the present value in the counter will be latched into the ccra registers and a stm interrupt generated. irrespective of what events occur on the stp pin the counter will continue to free run until the ston bit changes from high to low. when a ccrp compare match occurs the counter will reset back to zero; in this way the ccrp value can be used to control the maximum counter value. when a ccrp compare match occurs from comparator p, a stm interrupt will also be generated. counting the number of overfow interrupt signals from the ccrp can be a useful method in measuring long pulse widths. the stio1 and stio0 bits can select the active trigger edge on the stp pin to be a rising edge, falling edge or both edge types. if the stio1 and stio0 bits are both set high, then no capture operation will take place irrespective of what happens on the stp pin, however it must be noted that the counter will continue to run. the stcclr and stdpx bits are not used in this mode.
rev. 1.00 88 de?e??e? 01? ?01? rev. 1.00 89 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom counte? value yy ccrp ston stpau ccrp int. flag stmpf ccra int. flag stmaf ccra value ti?e counte? ?lea?ed ?y ccrp pause resu?e counte? reset stm [1:0] = 01 stm ?aptu?e pin stp xx counte? stop stio [1:0] value xx yy xx yy a?tive edge a?tive edge a?tive edge 00 C rising edge 01 C falling edge 10 C both edges 11 C disa?le captu?e capture input mode notes: 1. stm [1:0] = 01 and active edge set by the stio [1:0] bits 2. a stm capture input pin active edge transfers the counter value to ccra 3. stcclr bit not used 4. no output function C stoc and stpol bits are not used 5. ccrp determines the counter value and the counter has a maximum count value when ccrp is equal to zero
rev. 1.00 88 de?e??e? 01? ?01? rev. 1.00 89 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom periodic type tm C ptm the periodic type tm contains fve operating modes, which are compare match output, timer/ event counter, capture input, single pulse output and pwm output modes. the periodic tm can also be controlled with two external input pin and can drive an external output pin. ptm core ptm input pin ptm output pin 10-?it ptm ptck? ptp ptp f sys f sys /4 f h /64 f h /16 f sub ptck 000 001 010 011 100 101 110 111 ptck?~ptck0 10-?it count-up counte? 10-?it co?pa?ato? p ccrp ?0~?9 ?0~?9 10-?it co?pa?ato? a pton ptpau co?pa?ato? a mat?h co?pa?ato? p mat?h counte? clea? 0 1 output cont?ol pola?ity cont?ol ptp pin input/output ptp ptoc ptm1? ptm0 ptio1? ptio0 ptmaf inte??upt ptmpf inte??upt ptpol ccra ptcclr edge dete?to? ptio1? ptio0 f sub 1 0 ptcapts periodic type tm block diagram periodic type tm operation the size of periodic tm is 10-bit wide and its core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. there are also two internal comparators with the names, comparator a and comparator p. these comparators will compare the value in the counter with ccrp and ccra registers. the ccrp and ccra comparators are 10-bit wide whose value is compared with all counter bits. the only way of changing the value of the 10-bit counter using the application program is to clear the counter by changing the pton bit from low to high. the counter will also be cleared automatically by a counter overfow or a compare match with one of its associated comparators. when these conditions occur, a ptm interrupt signal will also usually be generated. the periodic type tm can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control two output pins. all operating setup conditions are selected using relevant internal registers. periodic type tm register description overall operation of the periodic tm is controlled using a series of registers. a read only register pair exists to store the internal counter 10-bit value, while two read/write register pairs exist to store the internal 10-bit ccra and ccrp value. the remaining two registers are control registers which setup the different operating and control modes.
rev. 1.00 90 de?e??e? 01? ?01? rev. 1.00 91 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom register name bit 7 6 5 4 3 2 1 0 ptmc0 ptpau ptck? ptck1 ptck0 pton ptmc1 ptm1 ptm0 ptio1 ptio0 ptoc ptpol ptcapts ptcclr ptmdl d? d6 d5 d4 d3 d? d1 d0 ptmdh d9 d8 ptmal d? d6 d5 d4 d3 d? d1 d0 ptmah d9 d8 ptmrpl ptrp? ptrp6 ptrp5 ptrp4 ptrp3 ptrp? ptrp1 ptrp0 ptmrph ptrp9 ptrp8 10-bit periodic tm register list ? ptmc0 register bit 7 6 5 4 3 2 1 0 na?e ptpau ptck? ptck1 ptck0 pton r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7 ptpau : ptm counter pause control 0: run 1: pause the counter can be paused by setting this bit high. clearing the bit to zero restores normal counter operation. when in a pause condition the ptm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 ptck2~ptck0 : select ptm counter clock 000: f /4 001: f 010: f /16 011: f /64 100: f 101: f 110: ptck rising edge clock 111: ptck falling edge clock these three bits are used to select the clock source for the ptm. the external pin clock source can be chosen to be active on the rising or falling edge. the clock source f is the system clock, while f and f are other internal clocks, the details of which can be found in the oscillator section. bit 3 pton : ptm counter on/off control 0: off 1: on this bit controls the overall on/off function of the ptm. setting the bit high enables the counter to run while clearing the bit disables the ptm. clearing this bit to zero will stop the counter from counting and turn off the ptm which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. if the ptm is in the compare match output mode or pwm output mode or single pulse output mode, then the ptm output pin will be reset to its initial condition, as specifed by the ptoc bit, when the pton bit changes from low to high. bit 2~0 unimplemented, read as "0"
rev. 1.00 90 de?e??e? 01? ?01? rev. 1.00 91 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom ? ptmc1 register bit 7 6 5 4 3 2 1 0 na?e ptm1 ptm0 ptio1 ptio0 ptoc ptpol ptcapts ptcclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 ptm1~ptm0 : select ptm operating mode 00: compare match output mode 01: capture input mode 10: pwm output mode or single pulse output mode 11: timer/counter mode these bits setup the required operating mode for the ptm. to ensure reliable operation the ptm should be switched off before any changes are made to the ptm1 and ptm0 bits. in the timer/counter mode, the ptm output pin control must be disabled. bit 5~4 ptio1~ptio0 : select ptp output function compare match output mode 00: no change 01: output low 10: output high 11: toggle output pwm output mode/single pulse output mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: single pulse output capture input mode 00: input capture at rising edge of ptp or ptck 01: input capture at falling edge of ptp or ptck 10: input capture at rising/falling edge of ptp or ptck 11: input capture disabled timer/counter mode unused these two bits are used to determine how the ptm output pin changes state when a certain condition is reached. the function that these bits select depends upon in which mode the ptm is running. in the compare match output mode, the ptio1 and ptio0 bits determine how the ptm output pin changes state when a compare match occurs from the comparator a. the ptm output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the ptm output pin should be setup using the ptoc bit in the ptmc1 register. note that the output level requested by the ptio1 and ptio0 bits must be different from the initial value setup using the ptoc bit otherwise no change will occur on the ptm output pin when a compare match occurs. after the ptm output pin changes state, it can be reset to its initial level by changing the level of the pton bit from low to high. in the pwm output mode, the ptio1 and ptio0 bits determine how the ptm output pin changes state when a certain compare match condition occurs. the ptm output function is modifed by changing these two bits. it is necessary to only change the values of the ptio1 and ptio0 bits only after the ptm has been switched off. unpredictable pwm outputs will occur if the ptio1 and ptio0 bits are changed when the ptm is running.
rev. 1.00 9? de?e??e? 01? ?01? rev. 1.00 93 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom bit 3 ptoc : ptm ptp output control compare match output mode 0: initial low 1: initial high pwm output mode/single pulse output mode 0: active low 1: active high this is the output control bit for the ptm output pin. its operation depends upon whether ptm is being used in the compare match output mode or in the pwm output mode/single pulse output mode. it has no effect if the ptm is in the timer/ counter mode. in the compare match output mode it determines the logic level of the ptm output pin before a compare match occurs. in the pwm output mode it determines if the pwm signal is active high or active low. in the single pulse output mode it determines the logic level of the ptm output pin when the pton bit changes from low to high. bit 2 ptpol : ptm ptp output polarity control 0: non-invert 1: invert this bit controls the polarity of the ptp output pin. when the bit is set high the ptm output pin will be inverted and not inverted when the bit is zero. it has no effect if the ptm is in the timer/counter mode. bit 1 ptcapts : ptm capture triiger source selection 0: from ptp pin 1: from ptck pin bit 0 ptcclr : ptm counter clear condition selection 0: comparator p match 1: comparator a match this bit is used to select the method which clears the counter. remember that the periodic tm contains two comparators, comparator a and comparator p, either of which can be selected to clear the internal counter. with the ptcclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low, the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow. a counter overfow clearing method can only be implemented if the ccrp bits are all cleared to zero. the ptcclr bit is not used in the pwm output, single pulse output or capture input mode. ? ptmdl register bit 7 6 5 4 3 2 1 0 na?e d? d6 d5 d4 d3 d? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 d7~d0 : ptm counter low byte register bit 7~bit 0 ptm 10-bit counter bit 7~bit 0 ? ptmdh register bit 7 6 5 4 3 2 1 0 na?e d9 d8 r/w r r por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 d9~d8 : ptm counter high byte register bit 1~bit 0 ptm 10-bit counter bit 9~bit 8
rev. 1.00 9? de?e??e? 01? ?01? rev. 1.00 93 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom ? ptmal register bit 7 6 5 4 3 2 1 0 na?e d? d6 d5 d4 d3 d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 d7~d0 : ptm ccra low byte register bit 7~bit 0 ptm 10-bit ccra bit 7~bit 0 ? ptmah register bit 7 6 5 4 3 2 1 0 na?e d9 d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 d9~d8 : ptm ccra high byte register bit 1~bit 0 ptm 10-bit ccra bit 9~bit 8 ? ptmrpl register bit 7 6 5 4 3 2 1 0 na?e ptrp? ptrp6 ptrp5 ptrp4 ptrp3 ptrp? ptrp1 ptrp0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 ptrp7~ptrp0 : ptm ccrp low byte register bit 7~bit 0 ptm 10-bit ccrp bit 7~bit 0 ? ptmrph register bit 7 6 5 4 3 2 1 0 na?e ptrp9 ptrp8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 ptrp9~ptrp8 : ptm ccrp high byte register bit 1~bit 0 ptm 10-bit ccrp bit 9~bit 8 periodic type tm operation modes the periodic type tm can operate in one of fve operating modes, compare match output mode, pwm output mode, single pulse output mode, capture input mode or timer/counter mode. the operating mode is selected using the ptm1 and ptm0 bits in the ptmc1 register. compare match output mode to select this mode, bits ptm1 and ptm0 in the ptmc1 register, should be set to 00 respectively. in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overfow, a compare match from comparator a and a compare match from comparator p. when the ptcclr bit is low, there are two ways in which the counter can be cleared. one is when a compare match from comparator p, the other is when the ccrp bits are all zero which allows the counter to overfow. here both ptmaf and ptmpf interrupt request fags for comparator a and comparator p respectively, will both be generated. if the ptcclr bit in the ptmc1 register is high then the counter will be cleared when a compare match occurs from comparator a. however, here only the ptmaf interrupt request fag will be
rev. 1.00 94 de?e??e? 01? ?01? rev. 1.00 95 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when ptcclr is high no ptmpf interrupt request fag will be generated. in the compare match output mode, the ccra can not be set to "0". if the ccra bits are all zero, the counter will overfow when its reaches its maximum 10-bit, 3ff hex, value, however here the ptmaf interrupt request fag will not be generated. as the name of the mode suggests, after a comparison is made, the ptm output pin will change state. the ptm output pin condition however only changes state when a ptmaf interrupt request fag is generated after a compare match occurs from comparator a. the ptmpf interrupt request fag, generated from a compare match occurs from comparator p, will have no effect on the ptm output pin. the way in which the ptm output pin changes state are determined by the condition of the ptio1 and ptio0 bits in the ptmc1 register. the ptm output pin can be selected using the ptio1 and ptio0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from comparator a. the initial condition of the ptm output pin, which is setup after the pton bit changes from low to high, is setup using the ptoc bit. note that if the ptio1 and ptio0 bits are zero then no pin change will take place. counte? value 0x3ff ccrp ccra pton ptpau ptpol ccrp int. flag ptmpf ccra int. flag ptmaf ptm o/p pin ti?e ccrp=0 ccrp > 0 counte? ove?flow ccrp > 0 counte? ?lea?ed ?y ccrp value pause resu?e stop counte? resta?t output pin set to initial level low if ptoc=0 output toggle with ptmaf flag note ptio [1:0] = 10 a?tive high output sele?t he?e ptio [1:0] = 11 toggle output sele?t output not affe?ted ?y ptmaf flag. re?ains high until ?eset ?y pton ?it output pin reset to initial value output ?ont?olled ?y othe? pin-sha?ed fun?tion output inve?ts when ptpol is high ptcclr = 0; ptm [1:0] = 00 compare match output mode C ptcclr = 0 notes: 1. with ptcclr=0, a comparator p match will clear the counter 2. the ptm output pin is controlled only by the ptmaf fag 3. the output pin is reset to its initial state by a pton bit rising edge
rev. 1.00 94 de?e??e? 01? ?01? rev. 1.00 95 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom counte? value 0x3ff ccrp ccra pton ptpau ptpol ccrp int. flag ptmpf ccra int. flag ptmaf ptm o/p pin ti?e ccra=0 ccra = 0 counte? ove?flow ccra > 0 counte? ?lea?ed ?y ccra value pause resu?e stop counte? resta?t output pin set to initial level low if ptoc=0 output toggle with ptmaf flag note ptio [1:0] = 10 a?tive high output sele?t he?e ptio [1:0] = 11 toggle output sele?t output not affe?ted ?y ptmaf flag. re?ains high until ?eset ?y pton ?it output pin reset to initial value output ?ont?olled ?y othe? pin-sha?ed fun?tion output inve?ts when ptpol is high ptmpf not gene?ated no ptmaf flag gene?ated on ccra ove?flow output does not ?hange ptcclr = 1; ptm [1:0] = 00 compare match output mode C ptcclr = 1 notes: 1. with ptcclr=1, a comparator a match will clear the counter 2. the ptm output pin is controlled only by the ptmaf fag 3. the output pin is reset to its initial state by a pton bit rising edge 4. a ptmpf fag is not generated when ptcclr =1
rev. 1.00 96 de?e??e? 01? ?01? rev. 1.00 9? de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom timer/counter mode to select this mode, bits ptm1 and ptm0 in the ptmc1 register should be set to 11 respectively. the timer/counter mode operates in an identical way to the compare match output mode generating the same interrupt flags. the exception is that in the timer/counter mode the ptm output pin is not used. therefore the above description and timing diagrams for the compare match output mode can be used to understand its function. as the ptm output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared functions. pwm output mode to select this mode, bits ptm1 and ptm0 in the ptmc1 register should be set to 10 respectively and also the ptio1 and ptio0 bits should be set to 10 respectively. the pwm function within the ptm is useful for applications which require functions such as motor control, heating control, illumination control, etc. by providing a signal of fxed frequency but of varying duty cycle on the ptm output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform is extremely fexible. in the pwm output mode, the ptcclr bit has no effect as the pwm period. both of the ccrp and ccra registers are used to generate the pwm waveform, one register is used to clear the internal counter and thus control the pwm waveform frequency, while the other one is used to control the duty cycle. the pwm waveform frequency and duty cycle can therefore be controlled by the values in the ccra and ccrp registers. an interrupt fag, one for each of the ccra and ccrp, will be generated when a compare match occurs from either comparator a or comparator p. the ptoc bit in the ptmc1 register is used to select the required polarity of the pwm waveform while the two ptio1 and ptio0 bits are used to enable the pwm output or to force the ptm output pin to a fxed high or low level. the ptpol bit is used to reverse the polarity of the pwm output waveform. ? 10-bit pwm output mode, edge-aligned mode ccrp 1~1023 0 pe?iod 1~10?3 10?4 duty ccra if f sys =16mhz, ptm clock source select f sys /4, ccrp=512 and ccra=128, the ptm pwm output frequency=(f sys /4)/512=f sys /2048=7.8125khz, duty=128/512=25%, if the duty value defned by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%.
rev. 1.00 96 de?e??e? 01? ?01? rev. 1.00 9? de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom counte? value ccrp ccra pton ptpau ptpol ccrp int. flag ptmpf ccra int. flag ptmaf ptm o/p pin (ptoc=1) ti?e counte? ?lea?ed ?y ccrp pause resu?e counte? stop if pton ?it low counte? reset when pton ?etu?ns high pwm duty cy?le set ?y ccra pwm ?esu?es ope?ation output ?ont?olled ?y othe? pin-sha?ed fun?tion output inve?ts when ptpol = 1 pwm pe?iod set ?y ccrp ptm o/p pin (ptoc=0) ptm [1:0] = 10 pwm output mode notes: 1. the counter is cleared by ccrp 2. a counter clear sets the pwm period 3. the internal pwm function continues running even when ptio [1:0] = 00 or 01 4. the ptcclr bit has no infuence on pwm operation
rev. 1.00 98 de?e??e? 01? ?01? rev. 1.00 99 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom single pulse output mode to select this mode, bits ptm1 and ptm0 in the ptmc1 register should be set to 10 respectively and also the ptio1 and ptio0 bits should be set to 11 respectively. the single pulse output mode, as the name suggests, will generate a single shot pulse on the ptm output pin. the trigger for the pulse output leading edge is a low to high transition of the pton bit, which can be implemented using the application program. however in the single pulse output mode, the pton bit can also be made to automatically change from low to high using the external ptck pin, which will in turn initiate the single pulse output. when the pton bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. the pton bit should remain high when the pulse is in its active state. the generated pulse trailing edge will be generated when the pton bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from comparator a. however a compare match from comparator a will also automatically clear the pton bit and thus generate the single pulse output trailing edge. in this way the ccra value can be used to control the pulse width. a compare match from comparator a will also generate a ptm interrupt. the counter can only be reset back to zero when the pton bit changes from low to high when the counter restarts. in the single pulse output mode ccrp is not used. the ptcclr is not used in this mode. pton ?it 0 1 s/w co??and set pton o? ptck pin t?ansition pton ?it 1 0 ccra t?ailing edge s/w co??and clr pton o? ccra co?pa?e mat?h ptp output pin pulse width = ccra value ccra leading edge single pulse generation
rev. 1.00 98 de?e??e? 01? ?01? rev. 1.00 99 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom counte? value ccrp ccra pton ptpau ptpol ccrp int. flag ptmpf ccra int. flag ptmaf ptm o/p pin (ptoc=1) ti?e counte? stopped ?y ccra pause resu?e counte? stops ?y softwa?e counte? reset when pton ?etu?ns high pulse width set ?y ccra output inve?ts when ptpol = 1 no ccrp inte??upts gene?ated ptm o/p pin (ptoc=0) ptck pin softwa?e t?igge? clea?ed ?y ccra ?at?h ptck pin t?igge? auto. set ?y ptck pin softwa?e t?igge? softwa?e clea? softwa?e t?igge? softwa?e t?igge? ptm [1:0] = 10 ; ptio [1:0] = 11 single pulse output mode notes: 1. counter stopped by ccra 2. ccrp is not used 3. the pulse triggered by the ptck pin or by setting the pton bit high 4. a ptck pin active edge will automatically set the pton bit high 5. in the single pulse output mode, ptio [1:0] must be set to "11" and can not be changed
rev. 1.00 100 de?e??e? 01? ?01? rev. 1.00 101 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom capture input mode to select this mode bits ptm1 and ptm0 in the ptmc1 register should be set to 01 respectively. this mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. the external signal is supplied on the ptp or ptck pin, selected by the ptcapts bit in the ptmc1 register. the input pin active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the ptio1 and ptio0 bits in the ptmc1 register. the counter is started when the pton bit changes from low to high which is initiated using the application program. when the required edge transition appears on the ptp or ptck pin the present value in the counter will be latched into the ccra registers and a ptm interrupt generated. irrespective of what events occur on the ptp or ptck pin the counter will continue to free run until the pton bit changes from high to low. when a ccrp compare match occurs the counter will reset back to zero; in this way the ccrp value can be used to control the maximum counter value. when a ccrp compare match occurs from comparator p, a ptm interrupt will also be generated. counting the number of overfow interrupt signals from the ccrp can be a useful method in measuring long pulse widths. the ptio1 and ptio0 bits can select the active trigger edge on the ptp or ptck pin to be a rising edge, falling edge or both edge types. if the ptio1 and ptio0 bits are both set high, then no capture operation will take place irrespective of what happens on the ptp or ptck pin, however it must be noted that the counter will continue to run. as the ptp or ptck pin is pin shared with other functions, care must be taken if the ptm is in the capture input mode. this is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. the ptcclr, ptoc and ptpol bits are not used in this mode.
rev. 1.00 100 de?e??e? 01? ?01? rev. 1.00 101 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom counte? value yy ccrp pton ptpau ccrp int. flag ptmpf ccra int. flag ptmaf ccra value ti?e counte? ?lea?ed ?y ccrp pause resu?e counte? reset ptm [1:0] = 01 ptm ?aptu?e pin ptp o? ptck xx counte? stop ptio [1:0] value xx yy xx yy a?tive edge a?tive edge a?tive edge 00 C rising edge 01 C falling edge 10 C both edges 11 C disa?le captu?e capture input mode notes: 1. ptm [1:0] = 01 and active edge set by the ptio [1:0] bits 2. a ptm capture input pin active edge transfers the counter value to ccra 3. ptcclr bit not used 4. no output function C ptoc and ptpol bits are not used 5. ccrp determines the counter value and the counter has a maximum count value when ccrp is equal to zero.
rev. 1.00 10? de?e??e? 01? ?01? rev. 1.00 103 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom analog to digital converter the need to interface to real world analog signals is a common requirement for many electronic systems. however, to properly process these signals by a microcontroller, they must first be converted into digital signals by a/d converters. by integrating the a/d conversion electronic circuitry into the microcontroller, the need for external components is reduced signifcantly with the corresponding follow-on benefts of lower costs and reduced component space requirements. a/d converter overview the device contains a multi-channel analog to digital converter which can directly interface to external analog signals, such as that from sensors or other control signals and convert these signals directly into a 12-bit digital value. it also can convert the internal signal into a 12-bit digital value. the external or internal analog signal to be converted is determined by the sains2~sains0 bits together with the sacs3~sacs0 bits. more detailed information about the a/d input signal is described in the "a/d converter control registers" and "a/d converter input signals" sections respectively. external input channels internal signals channel select bits 8: an0~an? v bg sains?~sains0? sacs3~sacs0 the accompanying block diagram shows the overall internal structure of the a/d converter, together with its associated registers. ace?~ace0 sacs3~sacs0 sains?~sains0 a/d conve?te? start adbz adcen v ss ? n (n=0~?) f sys sacks?~sacks0 v dd v dd savrs1~savrs0 adcen a/d refe?en?e voltage a/d data registe?s adrfs v bg gnd sadol sadoh a/d clo?k vref pin-sha?ed sele?tion an0 an1 an? a/d converter structure
rev. 1.00 10? de?e??e? 01? ?01? rev. 1.00 103 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom a/d converter register description overall operation of the a/d converter is controlled using several registers. a read only register pair exists to store the a/d converter data 12-bit value. the remaining two registers are control registers which setup the operating and control function of the a/d converter. register name bit 7 6 5 4 3 2 1 0 sadoh (adrfs=0) d11 d10 d9 d8 d? d6 d5 d4 sadol (adrfs=0) d3 d? d1 d0 sadoh (adrfs=1) d11 d10 d9 d8 sadol (adrfs=1) d? d6 d5 d4 d3 d? d1 d0 sadc0 start adbz adcen adrfs sacs3 sacs? sacs1 sacs0 sadc1 sains? sains1 sains0 savrs1 savrs0 sacks? sacks1 sacks0 acerl ace? ace6 ace5 ace4 ace3 ace? ace1 ace0 a/d converter register list a/d converter data registers C sadol, sadoh as the device contains an internal 12-bit a/d converter, it requires two data registers to store the converted value. these are a high byte register, known as sadoh, and a low byte register, known as sadol. after the conversion process takes place, these registers can be directly read by the microcontroller to obtain the digitised conversion value. as only 12 bits of the 16-bit register space is utilised, the format in which the data is stored is controlled by the adrfs bit in the sadc0 register as shown in the accompanying table. d0~d11 are the a/d conversion result data bits. any unused bits will be read as zero. note that a/d converter data register contents will be unchanged if the a/d converter is disabled. adrfs sadoh sadol 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 d11 d10 d9 d8 d? d6 d5 d4 d3 d? d1 d0 0 0 0 0 1 0 0 0 0 d11 d10 d9 d8 d? d6 d5 d4 d3 d? d1 d0 a/d data register pair a/d converter control registers C sadc0, sadc1, acerl to control the function and operation of the a/d converter, three control registers known as sadc0 and sadc1 and acerl are provided. these 8-bit registers defne functions such as the selection of which analog channel is connected to the internal a/d converter, the digitised data format, the a/d clock source as well as controlling the start function and monitoring the a/d converter busy status. as the device contains only one actual analog to digital converter hardware circuit, each of the external or internal analog signal inputs must be routed to the converter. the sacs3~sacs0 bits in the sadc0 register are used to determine which external channel input is selected to be converted. the sains2~sains0 bits in the sadc1 register are used to determine that the analog signal to be converted comes from the internal analog signal or external analog channel input. the acerl control register contains the ace7~ace0 bits which determine which pins on i/o port are used as analog inputs for the a/d converter input and which pins are not to be used as the a/d converter input. setting the corresponding bit high will select the a/d input function, clearing the bit to zero will select either the i/o or other pin-shared function. when the pin is selected to be an a/d input, its original function whether it is an i/o or other pin-shared function will be removed. in addition, any internal pull-high resistors connected to these pins will be automatically removed if the pin is selected to be an a/d input.
rev. 1.00 104 de?e??e? 01? ?01? rev. 1.00 105 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom ? sadc0 register bit 7 6 5 4 3 2 1 0 na?e start adbz adcen adrfs sacs3 sacs? sacs1 sacs0 r/w r/w r r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 start : start the a/d conversion 010: start a/d conversion this bit is used to initiate an a/d conversion process. the bit is normally low but if set high and then cleared low again, the a/d converter will initiate a conversion process. bit 6 adbz : a/d converter busy fag 0: no a/d conversion is in progress 1: a/d conversion is in progress this read only fag is used to indicate whether the a/d conversion is in progress or not. when the start bit is set from low to high and then to low again, the adbz fag will be set to 1 to indicate that the a/d conversion is initiated. the adbz fag will be cleared to 0 after the a/d conversion is complete. bit 5 adcen : a/d converter function enable control 0: disable 1: enable this bit controls the a/d internal function. this bit should be set to one to enable the a/d converter. if the bit is set low, then the a/d converter will be switched off reducing the device power consumption. when the a/d converter function is disabled, the contents of the a/d data register pair known as sadoh and sadol will not be cleared. bit 4 adrfs : a/d converter data format select 0: a/d converter data format sadoh = d[11:4]; sadol = d[3:0] 1: a/d converter data format sadoh = d[11:8]; sadol = d[7:0] this bit controls the format of the 12-bit converted a/d value in the two a/d data registers. details are provided in the a/d data register section. bit 3~0 sacs3~sacs0 : a/d converter external analog channel input select 0000: an0 0001: an1 0010: an2 0011: an3 0100: an4 0101: an5 0110: an6 0111: an7 1000~1111: un-existed channel, the external input is foating
rev. 1.00 104 de?e??e? 01? ?01? rev. 1.00 105 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom ? sadc1 register bit 7 6 5 4 3 2 1 0 na?e sains? sains1 sains0 savrs1 savrs0 sacks? sacks1 sacks0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~5 sains2~sains0 : a/d converter input signal select 000: external input C external analog channel input 001: internal input C internal bandgap reference voltage, v 010: internal input C unused, connected to ground 011: internal input C unused, connected to ground 100: internal input C unused, connected to ground 101~111: external input C external analog channel input care must be taken if the sains2~sains0 bits are set from "001" to "100" to select the internal analog signal to be converted. when the internal analog signal is selected to be converted, the external input pin must never be selected as the a/d input signal by properly setting the sacs3~sacs0 bits. otherwise, the external channel input will be connected together with the internal analog signal. this will result in unpredictable situations such as an irreversible damage. bit 4~3 savrs1~savrs0 : a/d converter reference voltage select 00:from external vref pin 01: internal a/d converter power, v 1x: from external vref pin these bits are used to select the a/d converter reference voltage. care must be taken if the savrs1~savrs0 bits are set to "01" to select the internal a/d converter power as the reference voltage source. when the internal a/d converter power is selected as the reference voltage, the vref pin cannot be confgured as the reference voltage input by properly confguring the corresponding control bits. otherwise, the external input voltage on vref pin will be connected to the internal a/d converter power. bit 2~0 sacks2~sacks0 : a/d conversion clock source select 000: f 001: f /2 010: f /4 011: f /8 100: f /16 101: f /32 110: f /64 111: f /128 these three bits are used to select the clock source for the a/d converter. ? acerl register bit 7 6 5 4 3 2 1 0 na?e ace? ace6 ace5 ace4 ace3 ace? ace1 ace0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 ace7 : defne pb3 is a/d input or not 0: not a/d input 1: a/d input, an7 bit 6 ace6 : defne pa7 is a/d input or not 0: not a/d input 1: a/d input, an6 bit 5 ace5 : defne pa6 is a/d input or not 0: not a/d input 1: a/d input, an5
rev. 1.00 106 de?e??e? 01? ?01? rev. 1.00 10? de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom bit 4 ace4 : defne pa5 is a/d input or not 0: not a/d input 1: a/d input, an4 bit 3 ace3 : defne pa4 is a/d input or not 0: not a/d input 1: a/d input, an3 bit 2 ace2 : defne pb2 is a/d input or not 0: not a/d input 1: a/d input, an2 bit 1 ace1 : defne pb1 is a/d input or not 0: not a/d input 1: a/d input, an1 bit 0 ace0 : defne pb0 is a/d input or not 0: not a/d input 1: a/d input, an0 a/d converter operation the start bit in the sadc0 register is used to start the a/d conversion. when the microcontroller sets this bit from low to high and then low again, an analog to digital conversion cycle will be initiated. the adbz bit in the sadc0 register is used to indicate whether the analog to digital conversion process is in progress or not. this bit will be automatically set to 1 by the microcontroller after an a/d conversion is successfully initiated. when the a/d conversion is complete, the adbz will be cleared to 0. in addition, the corresponding a/d interrupt request fag will be set in the interrupt control register, and if the interrupts are enabled, an appropriate internal interrupt signal will be generated. this a/d internal interrupt signal will direct the program flow to the associated a/d internal interrupt address for processing. if the a/d internal interrupt is disabled, the microcontroller can poll the adbz bit in the sadc0 register to check whether it has been cleared as an alternative method of detecting the end of an a/d conversion cycle. the clock source for the a/d converter, which originates from the system clock f , can be chosen to be either f or a subdivided version of f . the division ratio value is determined by the sacks2~sacks0 bits in the sadc1 register. although the a/d clock source is determined by the system clock f and by bits sacks2~sacks0, there are some limitations on the maximum a/d clock source speed that can be selected. as the recommended range of permissible a/d clock period, t adck , is from 0.5s to 10s, care must be taken for system clock frequencies. for example, as the system clock operates at a frequency of 8mhz, the sacks2~sacks0 bits should not be set to 000, 001 or 111. doing so will give a/d clock periods that are less than the minimum or larger than the maximum a/d clock period which may result in inaccurate a/d conversion values. refer to the following table for examples, where values marked with an asterisk * show where, depending upon the device, special care must be taken, as the values may be less or larger than the specifed a/d clock period range. f sys a/d clock period (t adck ) sacks[2:0] = 000 (f sys ) sacks[2:0] = 001 (f sys /2) sacks[2:0] = 010 (f sys /4) sacks[2:0] = 011 (f sys /8) sacks[2:0] = 100 (f sys /16) sacks[2:0] = 101 (f sys /32) sacks[2:0] = 110 (f sys /64) sacks[2:0] = 111 (f sys /128) 1mhz 1s 2s 4s 8s 16s * 32s * 64s * 128s * ?mhz 500ns 1s 2s 4s 8s 16s * 32s * 64s * 4mhz ?50ns * 500ns 1s 2s 4s 8s 16s * 32s * 8mhz 1?5ns * ?50ns * 500ns 1s 2s 4s 8s 16s * 1?mhz 83ns* 16?ns* 333ns* 66?ns 1.33s 2.67s 5.33s 10.67s* 16mhz 6?.5ns* 1?5ns* ?50ns* 500ns 1s 2s 4s 8s a/d clock period examples
rev. 1.00 106 de?e??e? 01? ?01? rev. 1.00 10? de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom controlling the power on/off function of the a/d converter circuitry is implemented using the adcen bit in the sadc0 register. this bit must be set high to power on the a/d converter. when the adcen bit is set high to power on the a/d converter internal circuitry a certain delay, as indicated in the timing diagram, must be allowed before an a/d conversion is initiated. even if no pins are selected for use as a/d inputs, if the adcen bit is high, then some power will still be consumed. in power conscious applications it is therefore recommended that the adcen is set low to reduce power consumption when the a/d converter function is not being used. a/d converter reference voltage the reference voltage supply to the a/d converter can be supplied from the power supply v dd , or from an external reference source supplied on pin vref. the desired selection is made using the savrs1 and savrs0 bits. when the savrs bit feld is set to "01", the a/d converter reference voltage will come from the v dd . otherwise, if the savrs bit feld is set to any other value except "01", the a/d converter reference voltage will come from the vref pin. as the vref pin is pin- shared with other functions, when the vref pin is selected as the reference voltage supply pin, the vref pin control bit vrefs should frst be set high to enable the vref pin function then the other pin functions will be disabled automatically. however, if the internal a/d converter power v dd is selected as the reference voltage, the vref pin must not be configured as the reference voltage input function to avoid the internal connection between the vref pin to a/d converter power v dd . the analog input values must not be allowed to exceed the value of the selected a/d reference voltage. a/d converter input signals all the external a/d analog channel input pins are pin-shared with the i/o pins as well as other functions. the ace7~ace0 bits in the acerl register, determine whether the input pins are setup as a/d converter analog input channel or whether they have other functions. if the ace7~ace0 bits for its corresponding pin is set high then the pin is setup to be as an a/d analog channel input, the original pin functions will be disabled. in this way, pins can be changed under program control to change their function between a/d inputs and other functions. all pull high resistors, which are setup through register programming, will be automatically disconnected if the pins are setup as a/d inputs. note that it is not necessary to frst setup the a/d pin as an input in the port control register to enable the a/d input as when the ace7~ace0 bits enable an a/d input, the status of the port control register will be overridden. the internal bandgap voltage can be connected to the a/d converter as the analog input signal by configuring the sains2~sains0 bits. if the external channel input is selected to be converted, the sains2~sains0 bits should be set to "000" or "101~111" and the sacs3~sacs0 bits can determine which external channel is selected. if the internal analog signal is selected to be converted, the sacs3~sacs0 bits must be confgured with an appropriate value to switch off the external analog channel input. otherwise, the internal analog signal will be connected together with the external channel input. this will result in unpredictable situations. sains[2:0] sacs[3:0] input signals description 000? 101~111 0000~0111 an0~an? exte?nal pin analog input 1000~1111 un-existed channel, input is foating. 001 1000~1111 v bg inte?nal bandgap ?efe?en?e voltage 010~100 1000~1111 gnd unused? ?onne?ted to g?ound a/d converter input signal selection
rev. 1.00 108 de?e??e? 01? ?01? rev. 1.00 109 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom conversion rate and timing diagram a complete a/d conversion contains two parts, data sampling and data conversion. the data sampling which is defned as t ads takes 4 a/d clock cycles and the data conversion takes 12 a/d clock cycles. therefore a total of 16 a/d clock cycles for an external input a/d conversion which is defned as t adc are necessary. maximum single a/d conversion rate = a/d clock period 16 the accompanying diagram shows graphically the various stages involved in an analog to digital conversion process and its associated timing. after an a/d conversion process has been initiated by the application program, the microcontroller internal hardware will begin to carry out the conversion, during which time the program can continue with other functions. the time taken for the a/d conversion is 16 t adck clock cycles where t adck is equal to the a/d clock period. adcen start adbz sacs[3:0] off on off on t on?st t ads a/d sa?pling ti?e t ads a/d sa?pling ti?e sta?t of a/d ?onve?sion sta?t of a/ d ?onve?sion sta?t of a/d ?onve?sion end of a/d ?onve?sion end of a/d ?onve?sion t adc a/d ?onve?sion ti?e t adc a/d ?onve?sion ti?e t adc a/d ?onve?sion ti?e 0011b 0010b 0000b 0001b a/d ?hannel swit?h a/d conversion timing summary of a/d conversion steps the following summarises the individual steps that should be executed in order to implement an a/d conversion process. ? step 1 select the required a/d conversion clock by correctly programming bits sacks2~sacks0 in the sadc1 register. ? step 2 enable the a/d by setting the adcen bit in the sadc0 register to 1. ? step 3 select which signal is to be connected to the internal a/d converter by correctly confguring the sains2~sains0 bits. select the external channel input to be converted, go to step 4. select the internal analog signal to be converted, go to step 5. ? step 4 if the a/d input signal comes from the external channel input selected by configuring the sains bit feld, the corresponding pins should be confgured as a/d input function by correctly programming the ace7~ace0 bits in the acerl register. the desired analog channel then should be selected by confguring the sacs bit feld. after this step, go to step 6.
rev. 1.00 108 de?e??e? 01? ?01? rev. 1.00 109 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom ? step 5 before the a/d input signal is selected to come from the internal analog signal by confguring the sains bit feld, the corresponding external input pin must be switched to a non-existed channel input by properly confgured the sacs3~sacs0 bits. the desired internal analog signal then can be selected by confguring the sains bit feld. after this step, go to step 6. ? step 6 select the reference voltage source by configuring the savrs1~savrs0 bits in the sadc1 register. ? step 7 select a/d converter output data format by setting the adrfs bit in the sadc0 register. ? step 8 if a/d conversion interrupt is used, the interrupt control registers must be correctly confgured to ensure the a/d interrupt function is active. the master interrupt control bit, emi, and the a/d conversion interrupt control bit, ade, must both be set high in advance. ? step 9 the a/d conversion procedure can now be initialized by setting the start bit from low to high and then low again. ? step 10 if a/d conversion is in progress, the adbz flag will be set high. after the a/d conversion process is complete, the adbz flag will go low and then the output data can be read from sadoh and sadol registers. note: when checking for the end of the conversion process, if the method of polling the adbz bit in the sadc0 register is used, the interrupt enable step above can be omitted. programming considerations during microcontroller operations where the a/d converter is not being used, the a/d internal circuitry can be switched off to reduce power consumption, by clearing bit adcen to 0 in the sadc0 register. when this happens, the internal a/d converter circuits will not consume power irrespective of what analog voltage is applied to their input lines. if the a/d converter input lines are used as normal i/o pins, then care must be taken as if the input voltage is not at a valid logic level, then this may lead to some increase in power consumption. a/d conversion function as the device contains a 12-bit a/d converter, its full-scale converted digitised value is equal to fffh. since the full-scale analog input value is equal to the actual a/d converter reference voltage, v ref , this gives a single bit analog input value of v ref divided by 4096. 1 lsb = v ref 4096 the a/d converter input voltage value can be calculated using the following equation: a/d input voltage = a/d converter output digital value (v ref 4096) the diagram shows the ideal transfer function between the analog input value and the digitised output value for the a/d converter. except for the digitised zero value, the subsequent digitised values will change at a point 0.5 lsb below where they would change without the offset, and the last full scale digitised value will change at a point 1.5 lsb below the v ref level. note that here the v ref voltage is the actual a/d converter reference voltage determined by the savrs feld.
rev. 1.00 110 de?e??e? 01? ?01? rev. 1.00 111 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom fffh ffeh ffdh 03h 0?h 01h 0 1 ? 3 4093 4094 4095 4096 v ref 4096 analog input voltage a/d conversion result 1.5 lsb 0.5 lsb ideal a/d transfer function a/d conversion programming examples the following two programming examples illustrate how to setup and implement an a/d conversion. in the frst example, the method of polling the adbz bit in the sadc0 register is used to detect when the conversion cycle is complete, whereas in the second example, the a/d interrupt is used to determine when the conversion is complete. example: using an adbz polling method to detect the end of conversion clr ade ; disable adc interrupt mov a,03h mov sadc1,a ; select f sys /8 as a/d clock set adcen mov a,0fh ; setup acerl to confgure pins an0~an3 mov acerl,a mov a,20h mov sadc0,a ; enable and connect an0 channel to a/d converter : start_conversion: clr start ; high pulse on start bit to initiate conversion set start ; reset a/d clr start ; start a/d polling_eoc: sz adbz ; poll the sadc0 register adbz bit to detect end of a/d conversion jmp polling_eoc ; continue polling mov a,sadol ; read low byte conversion result value mov sadol_buffer,a ; save result to user defned register mov a,sadoh ; read high byte conversion result value mov sadoh_buffer,a ; save result to user defned register : : jmp start_conversion ; start next a/d conversion
rev. 1.00 110 de?e??e? 01? ?01? rev. 1.00 111 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom example: using the interrupt method to detect the end of conversion clr ade ; disable adc interrupt mov a,03h mov sadc1,a ; select f sys /8 as a/d clock set adcen mov a, 0fh ; setup acerl to confgure pins an0~an3 mov acerl,a mov a,20h mov sadc0,a ; enable and connect an0 channel to a/d converter start_conversion: clr start ; high pulse on start bit to initiate conversion set start ; reset a/d clr start ; start a/d clr adf ; clear adc interrupt request fag set ade ; enable adc interrupt set emi ; enable global interrupt : : ; adc interrupt service routine adc_isr: mov acc_stack,a ; save acc to user defned memory mov a,status mov status_stack,a ; save status to user defned memory : : mov a,sadol ; read low byte conversion result value mov sadol_buffer,a ; save result to user defned register mov a,sadoh ; read high byte conversion result value mov sadoh_buffer,a ; save result to user defned register : : exit_int_isr: mov a,status_stack mov status,a ; restore status from user defned memory mov a,acc_stack ; restore acc from user defned memory reti
rev. 1.00 11 ? de?e??e? 01? ?01? rev. 1.00 113 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom comparator an analog comparator is contained within the device. the comparator function offers flexibility via their register controlled features such as power-down, polarity select, hysteresis etc. in sharing their pins with normal i/o pins the comparators do not waste precious i/o pins if there functions are otherwise unused. c+ cpol cout cint cos cx c- - + comparator comparator operation the device contains a comparator function which is used to compare two analog voltages and provide an output based on their input difference. full control over the internal comparator is provided via the control register, cpc. the comparator output is recorded via a bit in the control register, but can also be transferred output onto a shared i/o pin. additional comparator functions include polarity, hysteresis function and power down control. any pull-high resistors connected to the shared comparator input pins will be automatically disconnected when the corresponding comparator functional pins are selected. as the comparator inputs approach their switching level, some spurious output signals may be generated on the comparator output due to the slow rising or falling nature of the input signals. this can be minimised by the hysteresis function which will apply a small amount of positive feedback to the comparator. ideally the comparator should switch at the point where the positive and negative inputs signals are at the same voltage level. however, unavoidable input offsets introduce some uncertainties here. the offset calibration function, if executed, will minimize the switching offset value. comparator interrupt the comparator possesses its own interrupt function. when the comparator output changes state, its relevant interrupt fag will be set, and if the corresponding interrupt enable bit is set, then a jump to its relevant interrupt vector will be executed. note that it is the changing state of the cout bit and not the output pin which generates an interrupt. if the microcontroller is in the sleep or idle mode and the comparator is enabled, then if the external input lines cause the comparator output to change state, the resulting generated interrupt fag will also generate a wake-up. if it is required to disable a wake-up from occurring, then the interrupt fag should be frst set high before entering the sleep or idle mode. programming considerations if the comparator is enabled, it will remain active when the microcontroller enters the sleep or idle mode, however as it will consume a certain amount of power, the user may wish to consider disabling it before the sleep or idle mode is entered. as comparator pins are shared with normal i/o pins the i/o registers for these pins will be read as zero (port control register is "1") or read as port data register value (port control register is "0") if the comparator function is enabled.
rev. 1.00 11 ? de?e??e? 01? ?01? rev. 1.00 113 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom ? cpc register bit 7 6 5 4 3 2 1 0 na?e csel cen cpol cout cos cmpeg1 cmpeg0 chyen r/w r/w r/w r/w r r/w r/w r/w r/w por 1 0 0 0 0 0 0 1 bit 7 csel : select comparator pins or i/o pins 0: i/o pin select 1: comparator input pin c+ and c- selected this is the comparator input pin or i/o pin select bit. if the bit is high the comparator input pins will be enabled. as a result, these two pins will lose their i/o pin functions. any pull-high confguration options associated with the comparator shared pins will also be automatically disconnected. bit 6 cen : comparator on/off control 0: off 1: on this is the comparator on/off control bit. if the bit is zero the comparator will be switched off and no power consumed even if analog voltages are applied to its inputs. for power sensitive applications this bit should be cleared to zero if the comparator is not used or before the device enters the sleep or idle mode. bit 5 cpol : comparator output polarity 0: output non-invert 1: output invert this is the comparator polarity bit. if the bit is zero then the cout bit will refect the non-inverted output condition of the comparator. if the bit is high the comparator cout bit will be inverted. bit 4 cout : comparator output bit cpol=0 0: c+ < c- 1: c+ > c- cpol=1 0: c+ > c- 1: c+ < c- this bit stores the comparator output bit. the polarity of the bit is determined by the voltages on the comparator inputs and by the condition of the cpol bit. bit 3 cos : output path select ion 0: cx pin (compare output can output to cx pin) 1: i/o pin (compare output only internal use) bit 2~1 cmpeg1~cmpeg0 : comparator output interrupt edge trigger select ion 00: interrupt will be generated at rising edge of cout 01: interrupt will be generated at falling edge of cout 1x: interrupt will be generated at rising/ falling edge of cout bit 0 chyen : hysteresis control 0: off 1: on this is the hysteresis control bit and if set high will apply a limited amount of hysteresis to the comparator, as specifed in the comparator electrical characteristics table. the positive feedback induced by hysteresis reduces the effect of spurious switching near the comparator threshold.
rev. 1.00 114 de?e??e? 01? ?01? rev. 1.00 115 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom serial interface module C sim the device contains a serial interface module, which includes both the four-line spi interface or two-line i 2 c interface types, to allow an easy method of communication with external peripheral hardware. having relatively simple communication protocols, these serial interface types allow the microcontroller to interface to external spi or i 2 c based hardware such as sensors, flash or eeprom memory, etc. the sim interface pins are pin-shared with other i/o pins and therefore the sim interface functional pins must frst be selected using the relevant bit simen bit in the simc0 register. as both interface types share the same pins and registers, the choice of whether the spi or i 2 c type is used is made using the sim operating mode control bits, named sim2~sim0, in the simc0 register. these pull-high resistors of the sim pin-shared i/o pins are selected using pull-high control registers when the sim function is enabled and the corresponding pins are used as sim input pins. spi interface the spi interface is often used to communicate with external peripheral devices such as sensors, flash or eeprom memory devices, etc. originally developed by motorola, the four line spi interface is a synchronous serial data interface that has a relatively simple communication protocol simplifying the programming requirements when communicating with external hardware devices. the communication is full duplex and operates as a slave/master type, where the device can be either master or slave. although the spi interface specifcation can control multiple slave devices from a single master, the device provides only one scs pin. if the master needs to control multiple slave devices from a single master, the master can use i/o pin to select the slave devices. spi interface operation the spi interface is a full duplex synchronous serial data link. it is a four line interface with pin names sdi, sdo, sck and scs . pins sdi and sdo are the serial data input and serial data output lines, sck is the serial clock line and scs is the slave select line. as the spi interface pins are pin-shared with normal i/o pins and with the i 2 c function pins, the spi interface pins must frst be selected by setting the correct bits in the simc0 and simc2 registers. after the desired spi confguration has been set it can be disabled or enabled using the simen bit in the simc0 register. communication between devices connected to the spi interface is carried out in a slave/master mode with all data transfer initiations being implemented by the master. the master also controls the clock signal. as the device only contains a single scs pin only one slave device can be utilized. the scs pin is controlled by software, set csen bit to 1 to enable scs pin function, set csen bit to 0 the scs pin will be foating state. the spi function in this device offers the following features: ? full duplex synchronous data transfer ? both master and slave modes ? lsb frst or msb frst data transmission modes ? transmission complete fag ? rising or falling active clock edge the status of the spi interface pins is determined by a number of factors such as whether the device is in the master or slave mode and upon the condition of certain control bits such as csen and simen.
rev. 1.00 114 de?e??e? 01? ?01? rev. 1.00 115 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom sck spi maste? sdo sdi scs sck spi slave sdi sdo scs spi master/slave connection simd tx/rx shift registe? sdi pin clo?k edge/pola?ity cont?ol ckeg ckpolb clo?k sou??e sele?t f sys f sub ptm ccrp ?at?h f?equen?y/? sck pin csen busy status sdo pin scs pin data bus wcol trf simicf spi block diagram spi registers there are three internal registers which control the overall operation of the spi interface. these are the simd data register and two registers simc0 and simc2. note that the simc1 register is only used by the i 2 c interface. register name bit 7 6 5 4 3 2 1 0 simc0 sim? sim1 sim0 simdeb1 simdeb0 simen simicf simc? d? d6 ckpolb ckeg mls csen wcol trf simd d? d6 d5 d4 d3 d? d1 d0 spi register list ? simd register the simd register is used to store the data being transmitted and received. the same register is used by both the spi and i 2 c functions. before the device writes data to the spi bus, the actual data to be transmitted must be placed in the simd register. after the data is received from the spi bus, the device can read it from the simd register. any transmission or reception of data from the spi bus must be made via the simd register. bit 7 6 5 4 3 2 1 0 na?e d? d6 d5 d4 d3 d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x "x": unknown
rev. 1.00 116 de?e??e? 01? ?01? rev. 1.00 11 ? de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom there are also two control registers for the spi interface, simc0 and simc2. note that the simc2 register also has the name sima which is used by the i 2 c function. the simc1 register is not used by the spi function, only by the i 2 c function. register simc0 is used to control the enable/disable function and to set the data transmission clock frequency. register simc2 is used for other control functions such as lsb/msb selection, write collision fag, etc. ? simc0 register bit 7 6 5 4 3 2 1 0 na?e sim? sim1 sim0 simdeb1 simdeb0 simen simicf r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 0 0 0 0 bit 7~5 sim2~sim0 : sim operating mode control 000: spi master mode; spi clock is f /4 001: spi master mode; spi clock is f /16 010: spi master mode; spi clock is f /64 011: spi master mode; spi clock is f 100: spi master mode; spi clock is ptm ccrp match frequency/2 101: spi slave mode 110: i 2 c slave mode 111: non sim function these bits setup the overall operating mode of the sim function. as well as selecting if the i 2 c or spi function, they are used to control the spi master/slave selection and the spi master clock frequency. the spi clock is a function of the system clock but can also be chosen to be sourced from ptm and f . if the spi slave mode is selected then the clock will be supplied by an external master device. bit 4 unimplemented, read as "0" bit 3~2 simdeb1~simdeb0 : i 2 c debounce time selection 00: no debounce 01: 2 system clock debounce 1x: 4 system clock debounce bit 1 simen : sim enable control 0: disable 1: enable the bit is the overall on/off control for the sim interface. when the simen bit is cleared to zero to disable the sim interface, the sdi, sdo, sck and scs , or sda and scl lines will lose their spi or i 2 c function and the sim operating current will be reduced to a minimum value. when the bit is high the sim interface is enabled. the sim confguration option must have frst enabled the sim interface for this bit to be effective.if the sim is confgured to operate as an spi interface via the sim2~sim0 bits, the contents of the spi control registers will remain at the previous settings when the simen bit changes from low to high and should therefore be frst initialised by the application program. if the sim is confgured to operate as an i 2 c interface via the sim2~sim0 bits and the simen bit changes from low to high, the contents of the i 2 c control bits such as htx and txak will remain at the previous settings and should therefore be first initialised by the application program while the relevant i 2 c flags such as hcf, haas, hbb, srw and rxak will be set to their default states. bit 0 simicf : sim incomplete flag 0: sim incomplete condition not occurred 1: sim incomplete condition occured this bit is only available when the sim is confgured to operate in an spi slave mode. if the spi operates in the slave mode with the simen and csen bits both being set to 1 but the scs line is pulled high by the external master device before the spi data transfer is completely fnished, the simicf bit will be set to 1 together with the trf bit. when this condition occurs, the corresponding interrupt will occur if the interrupt function is enabled. however, the trf bit will not be set to 1 if the simicf bit is set to 1 by software application program.
rev. 1.00 116 de?e??e? 01? ?01? rev. 1.00 11 ? de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom ? simc2 register bit 7 6 5 4 3 2 1 0 na?e d? d6 ckpolb ckeg mls csen wcol trf r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 d7~d6 : undefned bits these bits can be read or written by the application program. bit 5 ckpolb : spi clock line base condition selection 0: the sck line will be high when the clock is inactive 1: the sck line will be low when the clock is inactive the ckpolb bit determines the base condition of the clock line, if the bit is high, then the sck line will be low when the clock is inactive. when the ckpolb bit is low, then the sck line will be high when the clock is inactive. bit 4 ckeg : spi sck clock active edge type selection ckpolb=0 0: sck is high base level and data capture at sck rising edge 1: sck is high base level and data capture at sck falling edge ckpolb=1 0: sck is low base level and data capture at sck falling edge 1: sck is low base level and data capture at sck rising edge the ckeg and ckpolb bits are used to setup the way that the clock signal outputs and inputs data on the spi bus. these two bits must be confgured before data transfer is executed otherwise an erroneous clock edge may be generated. the ckpolb bit determines the base condition of the clock line, if the bit is high, then the sck line will be low when the clock is inactive. when the ckpolb bit is low, then the sck line will be high when the clock is inactive. the ckeg bit determines active clock edge type which depends upon the condition of ckpolb bit. bit 3 mls : spi data shift order 0: lsb frst 1: msb frst this is the data shift select bit and is used to select how the data is transferred, either msb or lsb frst. setting the bit high will select msb frst and low for lsb frst. bit 2 csen : spi scs pin control 0: disable 1: enable the csen bit is used as an enable/disable for the scs pin. if this bit is low, then the scs pin will be disabled and placed into i/o pin or other pin-shared functions. if the bit is high, the scs pin will be enabled and used as a select pin. bit 1 wcol : spi write collision fag 0: no collision 1: collision the wcol fag is used to detect whether a data collision has occurred or not. if this bit is high, it means that data has been attempted to be written to the simd register duting a data transfer operation. this writing operation will be ignored if data is being transferred. this bit can be cleared to 0 by the application program. bit 0 trf : spi transmit/receive complete fag 0: spi data is being transferred 1: spi data transfer is completed the trf bit is the transmit/receive complete fag and is set to 1 automatically when an spi data transfer is completed, but must cleared to 0 by the application program. it can be used to generate an interrupt.
rev. 1.00 118 de?e??e? 01? ?01? rev. 1.00 119 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom spi communication after the spi interface is enabled by setting the simen bit high, then in the master mode, when data is written to the simd register, transmission/reception will begin simultaneously. when the data transfer is complete, the trf fag will be set automatically, but must be cleared using the application program. in the slave mode, when the clock signal from the master has been received, any data in the simd register will be transmitted and any data on the sdi pin will be shifted into the simd register. the master should output a scs signal to enable the slave devices before a clock signal is provided. the slave data to be transferred should be well prepared at the appropriate moment relative to the sck signal depending upon the confgurations of the ckpolb bit and ckeg bit. the accompanying timing diagram shows the relationship between the slave data and sck signal for various confgurations of the ckpolb and ckeg bits. the spi master mode will continue to function even in the idle mode if the selected spi clock source is running. sck (ckpolb=1? ckeg=0) sck (ckpolb=0? ckeg=0) sck (ckpolb=1? ckeg=1) sck (ckpolb=0? ckeg=1) scs sdo (ckeg=0) sdo (ckeg=1) sdi data captu?e w?ite to simd simen? csen=1 simen=1? csen=0 (exte?nal pull-high) d?/d0 d6/d1 d5/d? d4/d3 d3/d4 d?/d5 d1/d6 d0/d? d?/d0 d6/d1 d5/d? d4/d3 d3/d4 d?/d5 d1/d6 d0/d? spi master mode timing sck (ckpolb=1) sck (ckpolb=0) scs sdo sdi data captu?e w?ite to simd (sdo does not ?hange until fi?st sck edge) d?/d0 d6/d1 d5/d? d4/d3 d3/d4 d?/d5 d1/d6 d0/d? spi slave mode timing C ckeg = 0
rev. 1.00 118 de?e??e? 01? ?01? rev. 1.00 119 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom sck (ckpolb=1) sck (ckpolb=0) scs sdo sdi data captu?e d?/d0 d6/d1 d5/d? d4/d3 d3/d4 d?/d5 d1/d6 d0/d? w?ite to simd (sdo ?hanges as soon as w?iting o ??u?s; sdo is floating if scs=1) note: fo? spi slave ?ode? if simen= 1 and csen=0? spi is always ena?led and igno?es the scs level. spi slave mode timing C ckeg = 1 clea? wcol w?ite data into simd wcol=1? t?ans?ission ?o?pleted? (trf=1?) read data f?o? simd clea? trf end t?ansfe? finished? a spi t?ansfe? maste? o? slave ? simen=1 configu?e ckpolb? ckeg? csen and mls a sim[?:0]=000? 001? 010? 011 o? 100 sim[?:0]=101 maste? slave y y n n n y spi transfer control flow chart
rev. 1.00 1?0 de?e??e? 01? ?01? rev. 1.00 1?1 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom spi bus enable/disable to enable the spi bus, set csen=1 and scs =0, then wait for data to be written into the simd (txrx buffer) register. for the master mode, after data has been written to the simd (txrx buffer) register, then transmission or reception will start automatically. when all the data has been transferred, the trf bit should be set. for the slave mode, when clock pulses are received on sck, data in the txrx buffer will be shifted out or data on sdi will be shifted in. when the spi bus is disabled, sck, sdi, sdo and scs can become i/o pins or other pin-shared functions using the corresponding control bits. spi operation all communication is carried out using the 4-line interface for either master or slave mode. the csen bit in the simc2 register controls the overall function of the spi interface. setting this bit high will enable the spi interface by allowing the scs line to be active, which can then be used to control the spi interface. if the csen bit is low, the spi interface will be disabled and the scs line will be in a foating condition and can therefore not be used for control of the spi interface. if the csen bit and the simen bit in the simc0 are set high, this will place the sdi line in a foating condition and the sdo line high. if in master mode the sck line will be either high or low depending upon the clock polarity selection bit ckpolb in the simc2 register. if in slave mode the sck line will be in a foating condition. if the simen bit is low, then the bus will be disabled and scs , sdi, sdo and sck will all become i/o pins or the other functions using the corresponding control bits. in the master mode the master will always generate the clock signal. the clock and data transmission will be initiated after data has been written into the simd register. in the slave mode, the clock signal will be received from an external master device for both data transmission and reception. the following sequences show the order to be followed for data transfer in both master and slave mode. master mode: ? step 1 select the spi master mode and clock source using the sim2~sim0 bits in the simc0 control register. ? step 2 setup the csen bit and setup the mls bit to choose if the data is msb or lsb frst, this setting must be the same with the slave devices. ? step 3 setup the simen bit in the simc0 control register to enable the spi interface. ? step 4 for write operations: write the data to the simd register, which will actually place the data into the txrx buffer. then use the sck and scs lines to output the data. after this, go to step5. for read operations: the data transferred in on the sdi line will be stored in the txrx buffer until all the data has been received at which point it will be latched into the simd register. ? step 5 check the wcol bit if set high then a collision error has occurred so return to step 4. if equal to zero then go to the following step. ? step 6 check the trf bit or wait for a spi serial bus interrupt. ? step 7 read data from the simd register.
rev. 1.00 1?0 de?e??e? 01? ?01? rev. 1.00 1?1 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom ? step 8 clear trf. ? step 9 go to step 4. slave mode: ? step 1 select the spi slave mode using the sim2~sim0 bits in the simc0 control register ? step 2 setup the csen bit and setup the mls bit to choose if the data is msb or lsb frst, this setting must be the same with the master devices. ? step 3 setup the simen bit in the simc0 control register to enable the spi interface. ? step 4 for write operations: write the data to the simd register, which will actually place the data into the txrx buffer. then wait for the master clock sck and scs signal. after this, go to step5. for read operations: the data transferred in on the sdi line will be stored in the txrx buffer until all the data has been received at which point it will be latched into the simd register. ? step 5 check the wcol bit if set high then a collision error has occurred so return to step 4. if equal to zero then go to the following step. ? step 6 check the trf bit or wait for a spi serial bus interrupt. ? step 7 read data from the simd register. ? step 8 clear trf. ? step 9 go to step 4. error detection the wcol bit in the simc2 register is provided to indicate errors during data transfer. the bit is set by the spi serial interface but must be cleared by the application program. this bit indicates a data collision has occurred which happens if a write to the simd register takes place during a data transfer operation and will prevent the write operation from continuing. i 2 c interface the i 2 c interface is used to communicate with external peripheral devices such as sensors, eeprom memory etc. originally developed by philips, it is a two line low speed serial interface for synchronous serial data transfer. the advantage of only two lines for communication, relatively simple communication protocol and the ability to accommodate multiple devices on the same bus has made it an extremely popular interface type for many applications.
rev. 1.00 1?? de?e??e? 01? ?01? rev. 1.00 1?3 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom devi?e slave devi?e maste? devi?e slave vdd sda scl i 2 c master slave bus connection i 2 c interface operation the i 2 c serial interface is a two line interface, a serial data line, sda, and serial clock line, scl. as many devices may be connected together on the same bus, their outputs are both open drain types. for this reason it is necessary that external pull-high resistors are connected to these outputs. note that no chip select line exists, as each device on the i 2 c bus is identifed by a unique address which will be transmitted and received on the i 2 c bus. when two devices communicate with each other on the bidirectional i 2 c bus, one is known as the master device and one as the slave device. both master and slave can transmit and receive data, however, it is the master device that has overall control of the bus. for the device, which only operates in slave mode, there are two methods of transferring data on the i 2 c bus, the slave transmit mode and the slave receive mode. shift registe? t?ans?it/ re?eive cont?ol unit f sys f sub data bus i ? c add?ess registe? (sima) i ? c data registe? (simd) add?ess co?pa?ato? read/w?ite slave srw dete?t sta?t o? stop hbb ti?e-out cont?ol simtof add?ess mat?h C haas i ? c inte??upt de?oun?e ci??uit?y scl pin m u x txak data out msb simtoen add?ess mat?h simdeb[1:0] sda pin data in msb di?e?tion cont?ol htx 8-?it data t?ansfe? co?plete C hcf i 2 c block diagram the simdeb1 and simdeb0 bits determine the debounce time of the i 2 c interface. this uses the system clock to in effect add a debounce time to the external clock to reduce the possibility of glitches on the clock line causing erroneous operation. the debounce time, if selected, can be chosen to be either 2 or 4 system clocks. to achieve the required i 2 c data transfer speed, there exists a relationship between the system clock, f sys , and the i 2 c debounce time. for either the i 2 c standard or fast mode operation, users must take care of the selected system clock frequency and the confgured debounce time to match the criterion shown in the following table.
rev. 1.00 1?? de?e??e? 01? ?01? rev. 1.00 1?3 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom start signal f?o? maste? send slave add?ess and r/w ?it f?o? maste? a?knowledge f?o? slave send data ?yte f?o? maste? a?knowledge f?o? slave stop signal f?o? maste? i 2 c interface operation i 2 c debounce time selection i 2 c standard mode (100khz) i 2 c fast mode (400khz) no devoun?e f sys > ? mhz f sys > 5 mhz ? syste? ?lo?k de?oun?e f sys > 4 mhz f sys > 10 mhz 4 syste? ?lo?k de?oun?e f sys > 8 mhz f sys > ?0 mhz i 2 c minimum f sys frequency requirements i 2 c registers there are three control registers associated with the i 2 c bus, simc0, simc1 and simtoc, one slave address register, sima, and one data register, simd. the simd register, which is shown in the above spi section, is used to store the data being transmitted and received on the i 2 c bus. before the microcontroller writes data to the i 2 c bus, the actual data to be transmitted must be placed in the simd register. after the data is received from the i 2 c bus, the microcontroller can read it from the simd register. any transmission or reception of data from the i 2 c bus must be made via the simd register. note that the sima register also has the name simc2 which is used by the spi function. bit simen and bits sim2~sim0 in register simc0 are used by the i 2 c interface. register name bit 7 6 5 4 3 2 1 0 simc0 sim? sim1 sim0 simdeb1 simdeb0 simen simicf simc1 hcf haas hbb htx txak srw iamwu rxak sima sima6 sima5 sima4 sima3 sima? sim1 sima0 d0 simd d? d6 d5 d4 d3 d? d1 d0 simtoc simtoen simtof simtos5 simtos4 simtos3 simtos ? simtos1 simtos0 i 2 c register list ? simd register the simd register is used to store the data being transmitted and received. the same register is used by both the spi and i 2 c functions. before the device writes data to the i 2 c bus, the actual data to be transmitted must be placed in the simd register. after the data is received from the i 2 c bus, the device can read it from the simd register. any transmission or reception of data from the i 2 c bus must be made via the simd register.
rev. 1.00 1?4 de?e??e? 01? ?01? rev. 1.00 1?5 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom bit 7 6 5 4 3 2 1 0 na?e d? d6 d5 d4 d3 d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x "x": unknown ? sima register the sima register is also used by the spi interface but has the name simc2. the sima register is the location where the 7-bit slave address of the slave device is stored. bits 7~1 of the sima register defne the device slave address. bit 0 is not defned. when a master device, which is connected to the i 2 c bus, sends out an address, which matches the slave address in the sima register, the slave device will be selected. note that the sima register is the same register address as simc2 which is used by the spi interface. bit 7 6 5 4 3 2 1 0 na?e sima6 sima5 sima4 sima3 sima? sima1 sima0 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x "x": unknown bit 7~1 sima6~sima0 : i 2 c slave address sima6~sima0 is the i 2 c slave address bit 6~bit 0 bit 0 d0 : undefned bit the bit can be read or written by the application program. there are also three control registers for the i 2 c interface, simc0, simc1 and simtoc. the register simc0 is used to control the enable/disable function and to set the data transmission clock frequency.the simc1 register contains the relevant fags which are used to indicate the i 2 c communication status. the simtoc register is used to control the i 2 c bus time-out function which is described in the i 2 c time-out control section. ? simc0 register bit 7 6 5 4 3 2 1 0 na?e sim? sim1 sim0 simdeb1 simdeb0 simen simicf r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 0 0 0 0 bit 7~5 sim2~sim0 : sim operating mode control 000: spi master mode; spi clock is f /4 001: spi master mode; spi clock is f /16 010: spi master mode; spi clock is f /64 011: spi master mode; spi clock is f 100: spi master mode; spi clock is ptm ccrp match frequency/2 101: spi slave mode 110: i 2 c slave mode 111: non sim function these bits setup the overall operating mode of the sim function. as well as selecting if the i 2 c or spi function, they are used to control the spi master/slave selection and the spi master clock frequency. the spi clock is a function of the system clock but can also be chosen to be sourced from ptm and f . if the spi slave mode is selected then the clock will be supplied by an external master device. bit 4 unimplemented, read as "0" bit 3~2 simdeb1~simdeb0 : i 2 c debounce time selection 00: no debounce 01: 2 system clock debounce 1x: 4 system clock debounce
rev. 1.00 1?4 de?e??e? 01? ?01? rev. 1.00 1?5 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom bit 1 simen : sim enable control 0: disable 1: enable the bit is the overall on/off control for the sim interface. when the simen bit is cleared to zero to disable the sim interface, the sdi, sdo, sck and scs , or sda and scl lines will lose their spi or i 2 c function and the sim operating current will be reduced to a minimum value. when the bit is high the sim interface is enabled. the sim confguration option must have frst enabled the sim interface for this bit to be effective.if the sim is confgured to operate as an spi interface via the sim2~sim0 bits, the contents of the spi control registers will remain at the previous settings when the simen bit changes from low to high and should therefore be frst initialised by the application program. if the sim is confgured to operate as an i 2 c interface via the sim2~sim0 bits and the simen bit changes from low to high, the contents of the i 2 c control bits such as htx and txak will remain at the previous settings and should therefore be first initialised by the application program while the relevant i 2 c flags such as hcf, haas, hbb, srw and rxak will be set to their default states. bit 0 simicf : sim incomplete flag 0: sim incomplete condition not occurred 1: sim incomplete condition occured this bit is only available when the sim is confgured to operate in an spi slave mode. if the spi operates in the slave mode with the simen and csen bits both being set to 1 but the scs line is pulled high by the external master device before the spi data transfer is completely fnished, the simicf bit will be set to 1 together with the trf bit. when this condition occurs, the corresponding interrupt will occur if the interrupt function is enabled. however, the trf bit will not be set to 1 if the simicf bit is set to 1 by software application program. ? simc1 register bit 7 6 5 4 3 2 1 0 na?e hcf haas hbb htx txak srw iamwu rxak r/w r r r r/w r/w r/w r/w r por 1 0 0 0 0 0 0 1 bit 7 hcf : i 2 c bus data transfer completion fag 0: data is being transferred 1: completion of an 8-bit data transfer the hcf flag is the data transfer flag. this flag will be zero when data is being transferred. upon completion of an 8-bit data transfer the flag will go high and an interrupt will be generated. bit 6 haas : i 2 c address match fag 0: not address match 1: address match the haas fag is the address match fag. this fag is used to determine if the slave device address is the same as the master transmit address. if the addresses match then this bit will be high, if there is no match then the fag will be low. bit 5 hbb : i 2 c bus busy fag 0: i 2 c bus is not busy 1: i 2 c bus is busy the hbb fag is the i 2 c busy fag. this fag will be "1" when the i 2 c bus is busy which will occur when a start signal is detected. the fag will be set to "0" when the bus is free which will occur when a stop signal is detected. bit 4 htx : i 2 c slave device transmitter/receiver selection 0: slave device is the receiver 1: slave device is the transmitter
rev. 1.00 1?6 de?e??e? 01? ?01? rev. 1.00 1?? de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom bit 3 txak : i 2 c bus transmit acknowledge fag 0: slave send acknowledge fag 1: slave does not send acknowledge fag the txak bit is the transmit acknowledge fag. after the slave device receipt of 8-bits of data, this bit will be transmitted to the bus on the 9th clock from the slave device. the slave device must always set txak bit to "0" before further data is received. bit 2 srw : i 2 c slave read/write fag 0: slave device should be in receive mode 1: slave device should be in transmit mode the srw flag is the i 2 c slave read/write flag. this flag determines whether the master device wishes to transmit or receive data from the i 2 c bus. when the transmitted address and slave address is match, that is when the haas fag is set high, the slave device will check the srw fag to determine whether it should be in transmit mode or receive mode. if the srw fag is high, the master is requesting to read data from the bus, so the slave device should be in transmit mode. when the srw flag is zero, the master will write data to the bus, therefore the slave device should be in receive mode to read this data. bit 1 iamwu : i 2 c address match wake-up control 0: disable 1: enable C must be cleared to 0 by the application program after wake-up this bit should be set to 1 to enable the i 2 c address match wake up from the sleep or idle mode. if the iamwu bit has been set before entering either the sleep or idle mode to enable the i 2 c address match wake up, then this bit must be cleared to 0 by the application program after wake-up to ensure correction device operation. bit 0 rxak : i 2 c bus receive acknowledge fag 0: slave receives acknowledge fag 1: slave does not receive acknowledge fag the rxak flag is the receiver acknowledge flag. when the rxak flag is "0", it means that a acknowledge signal has been received at the 9th clock, after 8 bits of data have been transmitted. when the slave device in the transmit mode, the slave device checks the rxak fag to determine if the master receiver wishes to receive the next byte. the slave transmitter will therefore continue sending out data until the rxak fag is "1". when this occurs, the slave transmitter will release the sda line to allow the master to send a stop signal to release the i 2 c bus. i 2 c bus communication communication on the i 2 c bus requires four separate steps, a start signal, a slave device address transmission, a data transmission and finally a stop signal. when a start signal is placed on the i 2 c bus, all devices on the bus will receive this signal and be notifed of the imminent arrival of data on the bus. the frst seven bits of the data will be the slave address with the frst bit being the msb. if the address of the slave device matches that of the transmitted address, the haas bit in the simc1 register will be set and an i 2 c interrupt will be generated. after entering the interrupt service routine, the slave device must frst check the condition of the haas and simtof bits to determine whether the interrupt source originates from an address match, 8-bit data transfer completion or 2 c bus time-out occurrence. during a data transfer, note that after the 7-bit slave address has been transmitted, the following bit, which is the 8th bit, is the read/write bit whose value will be placed in the srw bit. this bit will be checked by the slave device to determine whether to go into transmit or receive mode. before any transfer of data to or from the i 2 c bus, the microcontroller must initialise the bus, the following are steps to achieve this: ? step 1 set the sim2~sim0 bits to "110" and simen bit to "1" in the simc0 register to enable the i 2 c bus. ? step 2 write the slave address of the device to the i 2 c bus address register sima. ? step 3 set the sime interrupt enable bit of the interrupt control register to enable the sim interrupt.
rev. 1.00 1?6 de?e??e? 01? ?01? rev. 1.00 1?? de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom set sim[?:0]=110 set simen w?ite slave add?ess to sima i ? c bus inte??upt=? clr sime poll simf to de?ide when to go to i ? c bus isr no yes set sime wait fo? inte??upt goto main p?og?a? goto main p?og?a? sta?t i 2 c bus initialisation flow chart i 2 c bus start signal the start signal can only be generated by the master device connected to the i 2 c bus and not by the slave device. this start signal will be detected by all devices connected to the i 2 c bus. when detected, this indicates that the i 2 c bus is busy and therefore the hbb bit will be set. a start condition occurs when a high to low transition on the sda line takes place when the scl line remains high. i 2 c slave address the transmission of a start signal by the master will be detected by all devices on the i 2 c bus. to determine which slave device the master wishes to communicate with, the address of the slave device will be sent out immediately following the start signal. all slave devices, after receiving this 7-bit address data, will compare it with their own 7-bit slave address. if the address sent out by the master matches the internal address of the microcontroller slave device, then an internal i 2 c bus interrupt signal will be generated. the next bit following the address, which is the 8th bit, defnes the read/write status and will be saved to the srw bit of the simc1 register. the slave device will then transmit an acknowledge bit, which is a low level, as the 9th bit. the slave device will also set the status fag haas when the addresses match. as an i 2 c bus interrupt can come from three sources, when the program enters the interrupt subroutine, the haas and simtof bits should be examined to see whether the interrupt source has come from a matching slave address, the completion of a data byte transfer or the i 2 c bus time-out occurrence. when a slave address is matched, the device must be placed in either the transmit mode and then write data to the simd register, or in the receive mode where it must implement a dummy read from the simd register to release the scl line. i 2 c bus read/write signal the srw bit in the simc1 register defnes whether the master device wishes to read data from the i 2 c bus or write data to the i 2 c bus. the slave device should examine this bit to determine if it is to be a transmitter or a receiver. if the srw fag is "1" then this indicates that the master device wishes to read data from the i 2 c bus, therefore the slave device must be setup to send data to the i 2 c bus as a transmitter. if the srw fag is "0" then this indicates that the master wishes to send data to the i 2 c bus, therefore the slave device must be setup to read data from the i 2 c bus as a receiver.
rev. 1.00 1?8 de?e??e? 01? ?01? rev. 1.00 1?9 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom i 2 c bus slave address acknowledge signal after the master has transmitted a calling address, any slave device on the i 2 c bus, whose own internal address matches the calling address, must generate an acknowledge signal. the acknowledge signal will inform the master that a slave device has accepted its calling address. if no acknowledge signal is received by the master then a stop signal must be transmitted by the master to end the communication. when the haas fag is high, the addresses have matched and the slave device must check the srw fag to determine if it is to be a transmitter or a receiver. if the srw fag is high, the slave device should be setup to be a transmitter so the htx bit in the simc1 register should be set to "1". if the srw fag is low, then the microcontroller slave device should be setup as a receiver and the htx bit in the simc1 register should be set to "0". i 2 c bus data and acknowledge signal the transmitted data is 8-bits wide and is transmitted after the slave device has acknowledged receipt of its slave address. the order of serial bit transmission is the msb frst and the lsb last. after receipt of 8-bits of data, the receiver must transmit an acknowledge signal, level "0", before it can receive the next data byte. if the slave transmitter does not receive an acknowledge bit signal from the master receiver, then the slave transmitter will release the sda line to allow the master to send a stop signal to release the i 2 c bus. the corresponding data will be stored in the simd register. if setup as a transmitter, the slave device must frst write the data to be transmitted into the simd register. if setup as a receiver, the slave device must read the transmitted data from the simd register. when the slave receiver receives the data byte, it must generate an acknowledge bit, known as txak, on the 9th clock. the slave device, which is setup as a transmitter will check the rxak bit in the simc1 register to determine if it is to send another data byte, if not then it will release the sda line and await the receipt of a stop signal from the master. sta?t scl sda scl sda 1 s=sta?t (1 ?it) sa=slave add?ess (? ?its) sr=srw ?it (1 ?it) m=slave devi?e send a?knowledge ?it (1 ?it) d=data (8 ?its) a=ack (rxak ?it fo? t?ans?itte?? txak ?it fo? ?e?eive?? 1 ?it) p=stop (1 ?it) 0 ack slave add?ess srw stop data ack 1101010 10010100 s sa sr m d a d a s sa sr m d a d a p i 2 c communication timing diagram note: when a slave address is matched, the device must be placed in either the transmit mode and then write data to the simd register, or in the receive mode where it must implement a dummy read from the simd register to release the scl line.
rev. 1.00 1?8 de?e??e? 01? ?01? rev. 1.00 1?9 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom sta?t simtof=1? set simtoen clr simtof reti haas=1? htx=1? srw=1? read f?o? simd to ?elease scl line reti rxak=1? w?ite data to simd to ?elease scl line clr htx clr txak du??y ?ead f?o? simd to ?elease scl line reti reti set htx w?ite data to simd to ?elease scl line reti clr htx clr txak du??y ?ead f?o? simd to ?elease scl line reti yes no no yes yes no yes no no yes i 2 c bus isr flow chart i 2 c time-out control in order to reduce the i 2 c lockup problem due to reception of erroneous clock sources, a time-out function is provided. if the clock source connected to the i 2 c bus is not received for a while, then the i 2 c circuitry and registers will be reset after a certain time-out period. the time-out counter starts to count on an i 2 c bus "start" & "address match"condition, and is cleared by an scl falling edge. before the next scl falling edge arrives, if the time elapsed is greater than the time-out period specifed by the simtoc register, then a time-out condition will occur. the time-out function will stop when an i 2 c "stop" condition occurs.
rev. 1.00 130 de?e??e? 01? ?01? rev. 1.00 131 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom sta?t scl sda scl sda 1 0 ack slave add?ess srw stop 1101010 10010100 i ? c ti?e-out ?ounte? sta?t i ? c ti?e-out ?ounte? ?eset on scl negative t?ansition i 2 c time-out when an i 2 c time-out counter overfow occurs, the counter will stop and the simtoen bit will be cleared to zero and the simtof bit will be set high to indicate that a time-out condition has occurred. the time-out condition will also generate an interrupt which uses the i 2 c interrrupt vector. when an i 2 c time-out occurs, the i 2 c internal circuitry will be reset and the registers will be reset into the following condition: registers after i 2 c time-out simd? sima? simc0 no ?hange simc1 reset to por ?ondition i 2 c register after time-out the simtof fag can be cleared by the application program. there are 64 time-out period selections which can be selected using the simtos bits in the simtoc register. the time-out duration is calculated by the formula: ((1~64) (32/f sub )). this gives a time-out period which ranges from about 1ms to 64ms. ? simtoc register bit 7 6 5 4 3 2 1 0 na?e simtoen simtof simtos5 simtos4 simtos3 simtos ? simtos1 simtos0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 : sim i 2 c time-out function control 0: disable 1: enable bit 6 : sim i 2 c time-out fag 0: no time-out occurred 1: time-out occurred bit 5~0 : sim i 2 c time-out period selection i 2 c time-out clock source is f sub /32. i 2 c time-out time is equal to (simtos[5:0]+1) (32/f sub ).
rev. 1.00 130 de?e??e? 01? ?01? rev. 1.00 131 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom uart interface the device contains an integrated full-duplex asynchronous serial communications uart interface that enables communication with external devices that contain a serial interface. the uart function has many features and can transmit and receive data serially by transferring a frame of data with eight or nine data bits per transmission as well as being able to detect errors when the data is overwritten or incorrectly framed. the uart function possesses its own internal interrupt which can be used to indicate when a reception occurs or when a transmission terminates. the integrated uart function contains the following features: ? full-duplex, asynchronous communication ? 8 or 9 bits character length ? even, odd or no parity options ? one or two stop bits ? baud rate generator with 8-bit prescaler ? parity, framing, noise and overrun error detection ? support for interrupt on address detect (last character bit=1) ? separately enabled transmitter and receiver ? 2-byte deep fifo receive data buffer ? rx pin wake-up function ? transmit and receive interrupts ? interrupts can be initialized by the following conditions: ? transmitter empty ? transmitter idle ? receiver full ? receiver overrun ? address mode detect msb lsb t?ans?itte? shift registe? (tsr) msb lsb re?eive? shift registe? (rsr) tx pin rx pin baud rate gene?ato? txr_rxr registe? txr_rxr registe? data to ?e t?ans?itted data ?e?eived buffe? f h mcu data bus uart data transfer block diagram
rev. 1.00 13? de?e??e? 01? ?01? rev. 1.00 133 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom uart external pins to communicate with an external serial interface, the internal uart has two external pins known as tx and rx. the tx and rx pins are the uart transmitter and receiver pins respectively. the tx and rx pin function should frst be selected by the ifs register before the uart function is used. along with the uarten bit, the txen and rxen bits, if set, will setup these pins to their respective tx output and rx input conditions and disable any pull-high resistor option which may exist on the tx and rx pins. when the tx or rx pin function is disabled by clearing the uarten, txen or rxen bit, the tx or rx pin will be set to a foating state. at this time whether the internal pull-high resistor is connected to the tx or rx pin or not is determined by the corresponding i/o pull-high function control bit. uart data transfer scheme the above block diagram shows the overall data transfer structure arrangement for the uart. the actual data to be transmitted from the mcu is first transferred to the txr_rxr register by the application program. the data will then be transferred to the transmit shift register from where it will be shifted out, lsb frst, onto the tx pin at a rate controlled by the baud rate generator. only the txr_rxr register is mapped onto the mcu data memory, the transmit shift register is not mapped and is therefore inaccessible to the application program. data to be received by the uart is accepted on the external rx pin, from where it is shifted in, lsb frst, to the receiver shift register at a rate controlled by the baud rate generator. when the shift register is full, the data will then be transferred from the shift register to the internal txr_rxr register, where it is buffered and can be manipulated by the application program. only the txr_ rxr register is mapped onto the mcu data memory, the receiver shift register is not mapped and is therefore inaccessible to the application program. it should be noted that the actual register for data transmission and reception only exists as a single shared register in the data memory. this shared register known as the txr_rxr register is used for both data transmission and data reception. uart status and control registers there are fve control registers associated with the uart function. the usr, ucr1 and ucr2 registers control the overall function of the uart, while the brg register controls the baud rate. the actual data to be transmitted and received on the serial interface is managed through the txr_ rxr data register. register name bit 7 6 5 4 3 2 1 0 usr perr nf ferr oerr ridle rxif tidle txif ucr1 uarten bno pren prt stops txbrk rx8 tx8 ucr? txen rxen brgh adden wake rie tiie teie txr_rxr txrx? txrx6 txrx5 txrx4 txrx3 txrx? txrx1 txrx0 brg brg? brg6 brg5 brg4 brg3 brg? brg1 brg0 uart register list
rev. 1.00 13? de?e??e? 01? ?01? rev. 1.00 133 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom ? txr_rxr register the txr_rxr register is the data register which is used to store the data to be transmitted on the tx pin or being received from the rx pin. bit 7 6 5 4 3 2 1 0 na?e txrx? txrx6 txrx5 txrx4 txrx3 txrx? txrx1 txrx0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x "x": unknown bit 7~0 txrx7~txrx0 : uart transmit/receive data bit 7~bit 0 ? usr register the usr register is the status register for the uart, which can be read by the program to determine the present status of the uart. all fags within the usr register are read only. further explanation on each of the fags is given below: bit 7 6 5 4 3 2 1 0 na?e perr nf ferr oerr ridle rxif tidle txif r/w r r r r r r r r por 0 0 0 0 1 0 1 1 bit 7 perr : parity error fag 0: no parity error is detected 1: parity error is detected the perr fag is the parity error fag. when this read only fag is "0", it indicates a parity error has not been detected. when the fag is "1", it indicates that the parity of the received word is incorrect. this error fag is applicable only if parity mode (odd or even) is selected. the fag can also be cleared to 0 by a software sequence which involves a read to the status register usr followed by an access to the txr_rxr data register. bit 6 nf : noise fag 0: no noise is detected 1: noise is detected the nf flag is the noise flag. when this read only flag is "0", it indicates no noise condition. when the fag is "1", it indicates that the uart has detected noise on the receiver input. the nf flag is set during the same cycle as the rxif flag but will not be set in the case of as overrun. the nf fag can be cleared to 0 by a software sequence which will involve a read to the status register usr followed by an access to the txr_rxr data register. bit 5 ferr : framing error fag 0: no framing error is detected 1: framing error is detected the ferr fag is the framing error fag. when this read only fag is "0", it indicates that there is no framing error. when the fag is "1", it indicates that a framing error has been detected for the current character. the fag can also be cleared to 0 by a software sequence which will involve a read to the status register usr followed by an access to the txr_rxr data register. bit 4 oerr : overrun error fag 0: no overrun error is detected 1: overrun error is detected the oerr fag is the overrun error fag which indicates when the receiver buffer has overfowed. when this read only fag is "0", it indicates that there is no overrun error. when the fag is "1", it indicates that an overrun error occurs which will inhibit further transfers to the txr_rxr receive data register. the fag is cleared to 0 by a software sequence, which is a read to the status register usr followed by an access to the txr_rxr data register.
rev. 1.00 134 de?e??e? 01? ?01? rev. 1.00 135 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom bit 3 ridle : receiver status 0: data reception is in progress (data being received) 1: no data reception is in progress (receiver is idle) the ridle fag is the receiver status fag. when this read only fag is "0", it indicates that the receiver is between the initial detection of the start bit and the completion of the stop bit. when the fag is "1", it indicates that the receiver is idle. between the completion of the stop bit and the detection of the next start bit, the ridle bit is "1" indicating that the uart receiver is idle and the rx pin stays in logic high condition. bit 2 rxif : receive txr_rxr data register status 0: txr_rxr data register is empty 1: txr_rxr data register has available data the rxif fag is the receive data register status fag. when this read only fag is "0", it indicates that the txr_rxr read data register is empty. when the flag is "1", it indicates that the txr_rxr read data register contains new data. when the contents of the shift register are transferred to the txr_rxr register, an interrupt is generated if rie=1 in the ucr2 register. if one or more errors are detected in the received word, the appropriate receive-related fags nf, ferr, and/or perr are set within the same clock cycle. the rxif fag will eventually be cleared to 0 when the usr register is read with rxif set, followed by a read from the txr_rxr register, and if the txr_ rxr register has no more new data available. bit 1 tidle : transmission idle 0: data transmission is in progress (data being transmitted) 1: no data transmission is in progress (transmitter is idle) the tidle flag is known as the transmission complete flag. when this read only flag is "0", it indicates that a transmission is in progress. this flag will be set high when the txif fag is "1" and when there is no transmit data or break character being transmitted. when tidle is equal to "1", the tx pin becomes idle with the pin state in logic high condition. the tidle fag is cleared to 0 by reading the usr register with tidle set and then writing to the txr_rxr register. the fag is not generated when a data character or a break is queued and ready to be sent. bit 0 txif : transmit txr_rxr data register status 0: character is not transferred to the transmit shift register 1: character has transferred to the transmit shift register (txr_rxr data register is empty) the txif fag is the transmit data register empty fag. when this read only fag is "0", it indicates that the character is not transferred to the transmitter shift register. when the fag is "1", it indicates that the transmitter shift register has received a character from the txr_rxr data register. the txif fag is cleared to 0 by reading the uart status register (usr) with txif set and then writing to the txr_rxr data register. note that when the txen bit is set, the txif fag bit will also be set since the transmit data register is not yet full.
rev. 1.00 134 de?e??e? 01? ?01? rev. 1.00 135 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom ? ucr1 register the ucr1 register together with the ucr2 register are the two uart control registers that are used to set the various options for the uart function, such as overall on/off control, parity control, data transfer bit length etc. further explanation on each of the bits is given below: bit 7 6 5 4 3 2 1 0 na?e uarten bno pren prt stops txbrk rx8 tx8 r/w r/w r/w r/w r/w r/w r/w r w por 0 0 0 0 0 0 x 0 "x": unknown bit 7 uarten : uart function enable control 0: disable uart. tx and rx pins are in a foating state 1: enable uart. tx and rx pins function as uart pins the uarten bit is the uart enable bit. when this bit is equal to "0", the uart will be disabled and the rx pin as well as the tx pin will be set in a foating state. when the bit is equal to "1", the uart will be enabled and the tx and rx pins will function as defned by the txen and rxen enable control bits. when the uart is disabled, it will empty the buffer so any character remaining in the buffer will be discarded. in addition, the value of the baud rate counter will be reset. if the uart is disabled, all error and status fags will be reset. also the txen, rxen, txbrk, rxif, oerr, ferr, perr and nf bits will be cleared to 0, while the tidle, txif and ridle bits will be set. other control bits in ucr1, ucr2 and brg registers will remain unaffected. if the uart is active and the uarten bit is cleared to 0, all pending transmissions and receptions will be terminated and the module will be reset as defned above. when the uart is re-enabled, it will restart in the same confguration. bit 6 bno : number of data transfer bits selection 0: 8-bit data transfer 1: 9-bit data transfer this bit is used to select the data length format, which can have a choice of either 8-bit or 9-bit format. when this bit is equal to "1", a 9-bit data length format will be selected. if the bit is equal to "0", then an 8-bit data length format will be selected. if 9-bit data length format is selected, then bits rx8 and tx8 will be used to store the 9th bit of the received and transmitted data respectively. bit 5 pren : parity function enable control 0: parity function is disabled 1: parity function is enabled this is the parity enable bit. when this bit is equal to "1", the parity function will be enabled. if the bit is equal to "0", then the parity function will be disabled. bit 4 prt : parity type selection bit 0: even parity for parity generator 1: odd parity for parity generator this bit is the parity type selection bit. when this bit is equal to "1", odd parity type will be selected. if the bit is equal to "0", then even parity type will be selected. bit 3 stops : number of stop bits selection 0: one stop bit format is used 1: two stop bits format is used this bit determines if one or two stop bits are to be used. when this bit is equal to "1", two stop bits are used. if this bit is equal to "0", then only one stop bit is used.
rev. 1.00 136 de?e??e? 01? ?01? rev. 1.00 13? de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom bit 2 txbrk : transmit break character 0: no break character is transmitted 1: break characters transmit the txbrk bit is the transmit break character bit. when this bit is "0", there are no break characters and the tx pin operates normally. when the bit is "1", there are transmit break characters and the transmitter will send logic zeros. when this bit is equal to "1", after the buffered data has been transmitted, the transmitter output is held low for a minimum of a 13-bit length and until the txbrk bit is reset. bit 1 rx8 : receive data bit 8 for 9-bit data transfer format (read only) this bit is only used if 9-bit data transfers are used, in which case this bit location will store the 9th bit of the received data known as rx8. the bno bit is used to determine whether data transfers are in 8-bit or 9-bit format. bit 0 tx8 : transmit data bit 8 for 9-bit data transfer format (write only) this bit is only used if 9-bit data transfers are used, in which case this bit location will store the 9th bit of the transmitted data known as tx8. the bno bit is used to determine whether data transfers are in 8-bit or 9-bit format. ? ucr2 register the ucr2 register is the second of the two uart control registers and serves several purposes. one of its main functions is to control the basic enable/disable operation of the uart transmitter and receiver as well as enabling the various uart interrupt sources. the register also serves to control the baud rate speed, receiver wake-up enable and the address detect enable. further explanation on each of the bits is given below: bit 7 6 5 4 3 2 1 0 na?e txen rxen brgh adden wake rie tiie teie r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 txen : uart transmitter enabled control 0: uart transmitter is disabled 1: uart transmitter is enabled the bit named txen is the transmitter enable bit. when this bit is equal to "0", the transmitter will be disabled with any pending data transmissions being aborted. in addition the buffers will be reset. in this situation the tx pin will be set in a foating state. if the txen bit is equal to "1" and the uarten bit is also equal to "1", the transmitter will be enabled and the tx pin will be controlled by the uart. clearing the txen bit during a transmission will cause the data transmission to be aborted and will reset the transmitter. if this situation occurs, the tx pin will be set in a foating state. bit 6 rxen : uart receiver enabled control 0: uart receiver is disabled 1: uart receiver is enabled the bit named rxen is the receiver enable bit. when this bit is equal to "0", the receiver will be disabled with any pending data receptions being aborted. in addition the receive buffers will be reset. in this situation the rx pin will be set in a foating state. if the rxen bit is equal to "1" and the uarten bit is also equal to "1", the receiver will be enabled and the rx pin will be controlled by the uart. clearing the rxen bit during a reception will cause the data reception to be aborted and will reset the receiver. if this situation occurs, the rx pin will be set in a foating state.
rev. 1.00 136 de?e??e? 01? ?01? rev. 1.00 13? de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom bit 5 brgh : baud rate speed selection 0: low speed baud rate 1: high speed baud rate the bit named brgh selects the high or low speed mode of the baud rate generator. this bit, together with the value placed in the baud rate register brg, controls the baud rate of the uart. if this bit is equal to "1", the high speed mode is selected. if the bit is equal to "0", the low speed mode is selected. bit 4 adden : address detect function enable control 0: address detect function is disabled 1: address detect function is enabled the bit named adden is the address detect function enable control bit. when this bit is equal to "1", the address detect function is enabled. when it occurs, if the 8th bit, which corresponds to rx7 if bno=0 or the 9th bit, which corresponds to rx8 if bno=1, has a value of "1", then the received word will be identifed as an address, rather than data. if the corresponding interrupt is enabled, an interrupt request will be generated each time the received word has the address bit set, which is the 8th or 9th bit depending on the value of bno. if the address bit known as the 8th or 9th bit of the received word is "0" with the address detect function being enabled, an interrupt will not be generated and the received data will be discarded. bit 3 wake : rx pin wake-up uart function enable control 0: rx pin wake-up uart function is disabled 1: rx pin wake-up uart function is enabled this bit is used to control the wake-up uart function when a falling edge on the rx pin occurs. note that this bit is only available when the uart clock (f h ) is switched off. there will be no rx pin wake-up uart function if the uart clock (f h ) exists. if the wake bit is set to 1 as the uart clock (f h ) is switched off, a uart wake- up request will be initiated when a falling edge on the rx pin occurs. when this request happens and the corresponding interrupt is enabled, an rx pin wake-up uart interrupt will be generated to inform the mcu to wake up the uart function by switching on the uart clock (f h ) via the application program. otherwise, the uart function can not resume even if there is a falling edge on the rx pin when the wake bit is cleared to 0. bit 2 rie : receiver interrupt enable control 0: receiver related interrupt is disabled 1: receiver related interrupt is enabled this bit enables or disables the receiver interrupt. if this bit is equal to "1" and when the receiver overrun fag oerr or receive data available fag rxif is set, the uart interrupt request fag will be set. if this bit is equal to "0", the uart interrupt request fag will not be infuenced by the condition of the oerr or rxif fags. bit 1 tiie : transmitter idle interrupt enable control 0: transmitter idle interrupt is disabled 1: transmitter idle interrupt is enabled this bit enables or disables the transmitter idle interrupt. if this bit is equal to "1" and when the transmitter idle fag tidle is set, due to a transmitter idle condition, the uart interrupt request fag will be set. if this bit is equal to "0", the uart interrupt request fag will not be infuenced by the condition of the tidle fag. bit 0 teie : transmitter empty interrupt enable control 0: transmitter empty interrupt is disabled 1: transmitter empty interrupt is enabled this bit enables or disables the transmitter empty interrupt. if this bit is equal to "1" and when the transmitter empty fag txif is set, due to a transmitter empty condition, the uart interrupt request flag will be set. if this bit is equal to "0", the uart interrupt request fag will not be infuenced by the condition of the txif fag.
rev. 1.00 138 de?e??e? 01? ?01? rev. 1.00 139 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom ? brg register bit 7 6 5 4 3 2 1 0 na?e brg? brg6 brg5 brg4 brg3 brg? brg1 brg0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x "x": unknown bit 7~0 brg7~brg0 : baud rate values by programming the brgh bit in ucr2 register which allows selection of the related formula described above and programming the required value in the brg register, the required baud rate can be setup. note: baud rate=f / [64 (n+1)] if brgh=0; baud rate=f / [16 (n+1)] if brgh=1. baud rate generator to setup the speed of the serial data communication, the uart function contains its own dedicated baud rate generator. the baud rate is controlled by its own internal free running 8-bit timer, the period of which is determined by two factors. the frst of these is the value placed in the baud rate register brg and the second is the value of the brgh bit with the control register ucr2. the brgh bit decides if the baud rate generator is to be used in a high speed mode or low speed mode, which in turn determines the formula that is used to calculate the baud rate. the value n in the brg register which is used in the following baud rate calculation formula determines the division factor. note that n is the decimal value placed in the brg register and has a range of between 0 and 255. ucr2 brgh bit 0 1 baud rate (br) f h / [64 (n+1)] f h / [16 (n+1)] by programming the brgh bit which allows selection of the related formula and programming the required value in the brg register, the required baud rate can be setup. note that because the actual baud rate is determined using a discrete value, n, placed in the brg register, there will be an error associated between the actual and requested value. the following example shows how the brg register value n and the error value can be calculated. calculating the baud rate and error values for a clock frequency of 4mhz, and with brgh cleared to zero determine the brg register value n, the actual baud rate and the error value for a desired baud rate of 4800. from the above table the desired baud rate br = f / [64 (n+1)] re-arranging this equation gives n = [f / (br64)] - 1 giving a value for n = [4000000 / (480064)] - 1 = 12.0208 to obtain the closest value, a decimal value of 12 should be placed into the brg register. this gives an actual or calculated baud rate value of br = 4000000 / [64 (12+1)] = 4808 therefore the error is equal to (4808 - 4800) / 4800 = 0.16%
rev. 1.00 138 de?e??e? 01? ?01? rev. 1.00 139 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom uart setup and control for data transfer, the uart function utilizes a non-return-to-zero, more commonly known as nrz, format. this is composed of one start bit, eight or nine data bits, and one or two stop bits. parity is supported by the uart hardware, and can be setup to be even, odd or no parity. for the most common data format, 8 data bits along with no parity and one stop bit, denoted as 8, n, 1, is used as the default setting, which is the setting at power-on. the number of data bits and stop bits, along with the parity, are setup by programming the corresponding bno, prt, pren, and stops bits in the ucr1 register. the baud rate used to transmit and receive data is setup using the internal 8-bit baud rate generator, while the data is transmitted and received lsb frst. although the uart transmitter and receiver are functionally independent, they both use the same data format and baud rate. in all cases stop bits will be used for data transmission. enabling/disabling the uart interface the basic on/off function of the internal uart function is controlled using the uarten bit in the ucr1 register. if the uarten, txen and rxen bits are set, then these two uart pins will act as normal tx output pin and rx input pin respectively. if no data is being transmitted on the tx pin, then it will default to a logic high value. clearing the uarten bit will disable the tx and rx pins and allow these two pins to be used as normal i/o or other pin-shared functional pins. when the uart function is disabled the buffer will be reset to an empty condition, at the same time discarding any remaining residual data. disabling the uart will also reset the error and status fags with bits txen, rxen, txbrk, rxif, oerr, ferr, perr and nf being cleared while bits tidle, txif and ridle will be set. the remaining control bits in the ucr1, ucr2 and brg registers will remain unaffected. if the uarten bit in the ucr1 register is cleared while the uart is active, then all pending transmissions and receptions will be immediately suspended and the uart will be reset to a condition as defned above. if the uart is then subsequently re-enabled, it will restart again in the same confguration. data, parity and stop bit selection the format of the data to be transferred is composed of various factors such as data bit length, parity on/off, parity type, address bits and the number of stop bits. these factors are determined by the setup of various bits within the ucr1 register. the bno bit controls the number of data bits which can be set to either 8 or 9, the prt bit controls the choice of odd or even parity, the pren bit controls the parity on/off function and the stops bit decides whether one or two stop bits are to be used. the following table shows various formats for data transmission. the address bit, which is the msb of the data byte, identifes the frame as an address character or data if the address detect function is enabled. the number of stop bits, which can be either one or two, is independent of the data length and is only used for the transmitter. there is only one stop bit for the receiver. start bit data bits address bit parity bit stop bit example of 8-bit data formats 1 8 0 0 1 1 ? 0 1 1 1 ? 1 0 1 example of 9-bit data formats 1 9 0 0 1 1 8 0 1 1 1 8 1 0 1 transmitter receiver data format
rev. 1.00 140 de?e??e? 01? ?01? rev. 1.00 141 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom the following diagram shows the transmit and receive waveforms for both 8-bit and 9-bit data formats. bit 0 8-bit data format bit 1 stop bit next sta?t bit sta?t bit pa?ity bit bit ? bit 3 bit 4 bit 5 bit 6 bit ? bit 0 9-bit data format bit 1 sta?t bit bit ? bit 3 bit 4 bit 5 bit 6 stop bit next sta?t bit pa?ity bit bit 8 bit ? uart transmitter data word lengths of either 8 or 9 bits can be selected by programming the bno bit in the ucr1 register. when bno bit is set, the word length will be set to 9 bits. in this case the 9th bit, which is the msb, needs to be stored in the tx8 bit in the ucr1 register. at the transmitter core lies the transmitter shift register, more commonly known as the tsr, whose data is obtained from the transmit data register, which is known as the txr_rxr register. the data to be transmitted is loaded into this txr_rxr register by the application program. the tsr register is not written to with new data until the stop bit from the previous transmission has been sent out. as soon as this stop bit has been transmitted, the tsr can then be loaded with new data from the txr_rxr register, if it is available. it should be noted that the tsr register, unlike many other registers, is not directly mapped into the data memory area and as such is not available to the application program for direct read/write operations. an actual transmission of data will normally be enabled when the txen bit is set, but the data will not be transmitted until the txr_rxr register has been loaded with data and the baud rate generator has defned a shift clock source. however, the transmission can also be initiated by frst loading data into the txr_rxr register, after which the txen bit can be set. when a transmission of data begins, the tsr is normally empty, in which case a transfer to the txr_rxr register will result in an immediate transfer to the tsr. if during a transmission the txen bit is cleared, the transmission will immediately cease and the transmitter will be reset. the tx output pin can then be confgured as the i/o or other pin-shared function. transmitting data when the uart is transmitting data, the data is shifted on the tx pin from the shift register, with the least signifcant bit frst. in the transmit mode, the txr_rxr register forms a buffer between the internal bus and the transmitter shift register. it should be noted that if 9-bit data format has been selected, then the msb will be taken from the tx8 bit in the ucr1 register. the steps to initiate a data transfer can be summarized as follows: ? make the correct selection of the bno, prt, pren and stops bits to defne the required word length, parity type and number of stop bits. ? setup the brg register to select the desired baud rate. ? set the txen bit to ensure that the tx pin is used as a uart transmitter pin. ? access the usr register and write the data that is to be transmitted into the txr_rxr register. note that this step will clear the txif bit. this sequence of events can now be repeated to send additional data. it should be noted that when txif=0, data will be inhibited from being written to the txr_rxr register. clearing the txif fag is always achieved using the following software sequence: 1. a usr register access 2. a txr_rxr register write execution
rev. 1.00 140 de?e??e? 01? ?01? rev. 1.00 141 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom the read-only txif flag is set by the uart hardware and if set indicates that the txr_rxr register is empty and that other data can now be written into the txr_rxr register without overwriting the previous data. if the teie bit is set then the txif fag will generate an interrupt. during a data transmission, a write instruction to the txr_rxr register will place the data into the txr_rxr register, which will be copied to the shift register at the end of the present transmission. when there is no data transmission in progress, a write instruction to the txr_rxr register will place the data directly into the shift register, resulting in the commencement of data transmission, and the txif bit being immediately set. when a frame transmission is complete, which happens after stop bits are sent or after the break frame, the tidle bit will be set. to clear the tidle bit the following software sequence is used: 1. a usr register access 2. a txr_rxr register write execution note that both the txif and tidle bits are cleared by the same software sequence. transmit break if the txbrk bit is set then break characters will be sent on the next transmission. break character transmission consists of a start bit, followed by 13n 0 bits and stop bits, where n=1, 2, etc. if a break character is to be transmitted then the txbrk bit must be frst set by the application program, and then cleared to generate the stop bits. transmitting a break character will not generate a transmit interrupt. note that a break condition length is at least 13 bits long. if the txbrk bit is continually kept at a logic high level then the transmitter circuitry will transmit continuous break characters. after the application program has cleared the txbrk bit, the transmitter will fnish transmitting the last break character and subsequently send out one or two stop bits. the automatic logic highs at the end of the last break character will ensure that the start bit of the next frame is recognized. uart receiver the uart is capable of receiving word lengths of either 8 or 9 bits. if the bno bit is set, the word length will be set to 9 bits with the msb being stored in the rx8 bit of the ucr1 register. at the receiver core lies the receive serial shift register, commonly known as the rsr. the data which is received on the rx external input pin is sent to the data recovery block. the data recovery block operating speed is 16 times that of the baud rate, while the main receive serial shifter operates at the baud rate. after the rx pin is sampled for the stop bit, the received data in rsr is transferred to the receive data register, if the register is empty. the data which is received on the external rx input pin is sampled three times by a majority detect circuit to determine the logic level that has been placed onto the rx pin. it should be noted that the rsr register, unlike many other registers, is not directly mapped into the data memory area and as such is not available to the application program for direct read/write operations. receiving data when the uart receiver is receiving data, the data is serially shifted in on the external rx input pin, lsb frst. in the read mode, the txr_rxr register forms a buffer between the internal bus and the receiver shift register. the txr_rxr register is a two byte deep fifo data buffer, where two bytes can be held in the fifo while a third byte can continue to be received. note that the application program must ensure that the data is read from txr_rxr before the third byte has been completely shifted in, otherwise this third byte will be discarded and an overrun error oerr will be subsequently indicated. the steps to initiate a data transfer can be summarized as follows:
rev. 1.00 14? de?e??e? 01? ?01? rev. 1.00 143 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom ? make the correct selection of bno, prt and pren bits to defne the word length, parity type. ? setup the brg register to select the desired baud rate. ? set the rxen bit to ensure that the rx pin is used as a uart receiver pin. at this point the receiver will be enabled which will begin to look for a start bit. when a character is received the following sequence of events will occur: ? the rxif bit in the usr register will be set when the txr_rxr register has data available. there will be at most one more character available before an overrun error occurs. ? when the contents of the shift register have been transferred to the txr_rxr register, then if the rie bit is set, an interrupt will be generated. ? if during reception, a frame error, noise error, parity error, or an overrun error has been detected, then the error fags can be set. the rxif bit can be cleared using the following software sequence: 1. a usr register access 2. a txr_rxr register read execution receive break any break character received by the uart will be managed as a framing error. the receiver will count and expect a certain number of bit times as specifed by the values programmed into the bno bit plus one stop bit. if the break is much longer than 13 bit times, the reception will be considered as complete after the number of bit times specifed by bno plus one stop bit. the rxif bit is set, ferr is set, zeros are loaded into the receive data register, interrupts are generated if appropriate and the ridle bit is set. a break is regarded as a character that contains only zeros with the ferr fag set. if a long break signal has been detected, the receiver will regard it as a data frame including a start bit, data bits and the invalid stop bit and the ferr fag will be set. the receiver must wait for a valid stop bit before looking for the next start bit. the receiver will not make the assumption that the break condition on the line is the next start bit. the break character will be loaded into the buffer and no further data will be received until stop bits are received. it should be noted that the ridle read only fag will go high when the stop bits have not yet been received. the reception of a break character on the uart registers will result in the following: ? the framing error fag, ferr, will be set. ? the receive data register, txr_rxr, will be cleared. ? the oerr, nf, perr, ridle or rxif fags will possibly be set. idle status when the receiver is reading data, which means it will be in between the detection of a start bit and the reading of a stop bit, the receiver status fag in the usr register, otherwise known as the ridle fag, will have a zero value. in between the reception of a stop bit and the detection of the next start bit, the ridle fag will have a high value, which indicates the receiver is in an idle condition. receiver interrupt the read only receive interrupt fag rxif in the usr register is set by an edge generated by the receiver. an interrupt is generated if rie=1, when a word is transferred from the receive shift register, rsr, to the receive data register, txr_rxr. an overrun error can also generate an interrupt if rie=1.
rev. 1.00 14? de?e??e? 01? ?01? rev. 1.00 143 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom managing receiver errors several types of reception errors can occur within the uart module, the following section describes the various types and how they are managed by the uart. overrun error C oerr the txr_rxr register is composed of a two byte deep fifo data buffer, where two bytes can be held in the fifo register, while a third byte can continue to be received. before this third byte has been entirely shifted in, the data should be read from the txr_rxr register. if this is not done, the overrun error fag oerr will be consequently indicated. in the event of an overrun error occurring, the following will happen: ? the oerr fag in the usr register will be set. ? the txr_rxr contents will not be lost. ? the shift register will be overwritten. ? an interrupt will be generated if the rie bit is set. the oerr fag can be cleared by an access to the usr register followed by a read to the txr_ rxr register. noise error C nf over-sampling is used for data recovery to identify valid incoming data and noise. if noise is detected within a frame the following will occur: ? the read only noise fag, nf, in the usr register will be set on the rising edge of the rxif bit. ? data will be transferred from the shift register to the txr_rxr register. ? no interrupt will be generated. however this bit rises at the same time as the rxif bit which itself generates an interrupt. note that the nf fag is reset by a usr register read operation followed by a txr_rxr register read operation. framing error C ferr the read only framing error fag, ferr, in the usr register, is set if a zero is detected instead of stop bits. if two stop bits are selected, both stop bits must be high; otherwise the ferr fag will be set. the ferr fag and the received data will be recorded in the usr and txr_rxr registers respectively, and the fag is cleared in any reset. parity error C perr the read only parity error fag, perr, in the usr register, is set if the parity of the received word is incorrect. this error fag is only applicable if the parity is enabled, pren = 1, and if the parity type, odd or even is selected. the read only perr fag and the received data will be recorded in the usr and txr_rxr registers respectively. it is cleared on any reset, it should be noted that the fags, ferr and perr, in the usr register should frst be read by the application program before reading the data word.
rev. 1.00 144 de?e??e? 01? ?01? rev. 1.00 145 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom uart interrupt structure several individual uart conditions can generate a uart interrupt. when these conditions exist, a low pulse will be generated to get the attention of the microcontroller. these conditions are a transmitter data register empty, transmitter idle, receiver data available, receiver overrun, address detect and an rx pin wake-up. when any of these conditions are created, if the global interrupt enable bit and its corresponding interrupt control bit are enabled and the stack is not full, the program will jump to its corresponding interrupt vector where it can be serviced before returning to the main program. four of these conditions have the corresponding usr register fags which will generate a uart interrupt if its associated interrupt enable control bit in the ucr2 register is set. the two transmitter interrupt conditions have their own corresponding enable control bits, while the two receiver interrupt conditions have a shared enable control bit. these enable bits can be used to mask out individual uart interrupt sources. the address detect condition, which is also a uart interrupt source, does not have an associated fag, but will generate a uart interrupt when an address detect condition occurs if its function is enabled by setting the adden bit in the ucr2 register. an rx pin wake-up, which is also a uart interrupt source, does not have an associated fag, but will generate a uart interrupt if the uart clock (f h ) source is switched off and the wake and rie bits in the ucr2 register are set when a falling edge on the rx pin occurs. note that the usr register flags are read only and cannot be cleared or set by the application program, neither will they be cleared when the program jumps to the corresponding interrupt servicing routine, as is the case for some of the other interrupts. the flags will be cleared automatically when certain actions are taken by the uart, the details of which are given in the uart register section. the overall uart interrupt can be disabled or enabled by the related interrupt enable control bits in the interrupt control registers of the microcontroller to decide whether the interrupt requested by the uart module is masked out or allowed. t?ans?itte? e?pty flag txif unsr registe? t?ans?itte? idle flag tidle re?eive? ove??un flag oerr re?eive? data availa?le rxif adden rx pin wake-up wake 0 1 0 1 rx? if bno=0 rx8 if bno=1 ucr? registe? rie 0 1 tiie 0 1 teie 0 1 uart inte??upt request flag urf ucr? registe? ure emi 0 1 inte??upt signal to mcu uart interrupt structure
rev. 1.00 144 de?e??e? 01? ?01? rev. 1.00 145 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom address detect mode setting the address detect mode bit, adden, in the ucr2 register, enables this special mode. if this bit is enabled then an additional qualifer will be placed on the generation of a receiver data available interrupt, which is requested by the rxif fag. if the adden bit is enabled, then when data is available, an interrupt will only be generated, if the highest received bit has a high value. note that the ure and emi interrupt enable bits must also be enabled for correct interrupt generation. this highest address bit is the 9th bit if bno=1 or the 8th bit if bno=0. if this bit is high, then the received word will be defned as an address rather than data. a data available interrupt will be generated every time the last bit of the received word is set. if the adden bit is not enabled, then a receiver data available interrupt will be generated each time the rxif fag is set, irrespective of the data last bit status. the address detect mode and parity enable are mutually exclusive functions. therefore if the address detect mode is enabled, then to ensure correct operation, the parity function should be disabled by resetting the parity enable bit pren to zero. adden bit 9 if bno=1, bit 8 if bno=0 uart interrupt generated 0 0 1 1 0 1 adden bit function uart power down and wake-up when the uart clock, f h , is switched off, the uart will cease to function. if the mcu switches off the uart clock, f h , and enters the power down mode while a transmission is still in progress, then the transmission will be paused until the uart clock source derived from the microcontroller is activated. in a similar way, if the mcu switches off the uart clock f h and enters the idle or sleep mode by executing the "halt" instruction while receiving data, then the reception of data will likewise be paused. when the mcu enters the idle or sleep mode, note that the usr, ucr1, ucr2, transmit and receive registers, as well as the brg register will not be affected. it is recommended to make sure frst that the uart data transmission or reception has been fnished before the microcontroller enters the idle or sleep mode. the uart function contains a receiver rx pin wake-up function, which is enabled or disabled by the wake bit in the ucr2 register. if this bit, along with the uart enable bit, uarten, the receiver enable bit, rxen and the receiver interrupt bit, rie, are all set when the mcu enters the power down mode with the uart clock f h being switched off, then a falling edge on the rx pin will initiate an rx pin wake-up uart interrupt. note that as it takes certain system clock cycles after a wake-up, before normal microcontroller operation resumes, any data received during this time on the rx pin will be ignored. for a uart wake-up interrupt to occur, in addition to the bits for the wake-up being set, the global interrupt enable bit, emi, and the uart interrupt enable bit, ure, must be set. if the emi and ure bits are not set then only a wake up event will occur and no interrupt will be generated. note also that as it takes certain system clock cycles after a wake-up before normal microcontroller resumes, the uart interrupt will not be generated until after this time has elapsed.
rev. 1.00 146 de?e??e? 01? ?01? rev. 1.00 14? de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom interrupts interrupts are an important part of any microcontroller system. when an external event or an internal function such as a timer module require or an a/d converter requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. the device contains several external interrupt and internal interrupt functions. the external interrupt is generated by the action of the external intn pin, while the internal interrupts are generated by various internal functions such as the tms, comparator, time bases, lvd, eeprom, a/d converter, sim and uart. interrupt registers overall interrupt control, which basically means the setting of request flags when certain microcontroller conditions occur and the setting of interrupt enable bits by the application program, is controlled by a series of registers, located in the special purpose data memory, as shown in the accompanying table. the number of registers falls into three categories. the first is the intc0~intc2 registers which setup the primary interrupts, the second is the mfi0~mfi2 register which setup the multi-function interrupt. finally there is an integ register to setup the external interrupt trigger edge type. each register contains a number of enable bits to enable or disable individual registers as well as interrupt flags to indicate the presence of an interrupt request. the naming convention of these follows a specifc pattern. first is listed an abbreviated interrupt type, then the (optional) number of that interrupt followed by either an "e" for enable/disable bit or "f" for request fag. function enable bit request flag notes glo?al emi intn pin intne intnf n=0~1 co?pa?ato? cpe cpf multi-fun?tion mfne mfnf n=0~? a/d conve?te? ade adf ti ?e base tbne tbnf n=0~1 lvd lve lvf eeprom dee def sim sime simf uart ure urf ctm ctmpe ctmpf ctmae ctmaf stm stmpe stmpf stmae stmaf ptm ptmpe ptmpf ptmae ptmaf interrupt register bit naming conventions
rev. 1.00 146 de?e??e? 01? ?01? rev. 1.00 14? de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom register name bit 7 6 5 4 3 2 1 0 integ int1s1 int1s0 int0s1 int0s0 intc0 mf0f cpf int0f mf0e cpe int0e emi intc1 tb0f adf mf?f mf1f tb0e ade mf?e mf1e intc? urf simf int1f tb1f ure sime int1e tb1e mfi0 stmaf stmpf stmae stmpe mfi1 ctmaf ctmpf ptmaf ptmpf ctmae ctmpe ptmae ptmpe mfi? def lvf dee lve interrupt register list ? integ register bit 7 6 5 4 3 2 1 0 na?e int1s1 int1s0 int0s1 int0s0 r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~4 unimplemented, read as "0" bit 3~2 int1s1~int1s0 : nterrupt edge control for int1 pin 00: disable 01: rising edge 10: falling edge 11: both rising and falling edges bit 1~0 int0s1~int0s0 : nterrupt edge control for int0 pin 00: disable 01: rising edge 10: falling edge 11: both rising and falling edges ? intc0 register bit 7 6 5 4 3 2 1 0 na?e mf0f cpf int0f mf0e cpe int0e emi r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 unimplemented, read as "0" bit 6 mf0f : multi-function 0 nterrupt equest flag 0: no request 1: interrupt request bit 5 cpf : comparator interrupt request fag 0: no request 1: interrupt request bit 4 int0f : int0 nterrupt equest flag 0: no request 1: interrupt request bit 3 mf0e : multi-function 0 nterrupt c ontrol 0: disable 1: enable bit 2 cpe : comparator nterrupt control 0: disable 1: enable
rev. 1.00 148 de?e??e? 01? ?01? rev. 1.00 149 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom bit 1 int0e : int0 i nterrupt c ontrol 0: disable 1: enable bit 0 emi : global i nterrupt c ontrol 0: disable 1: enable ? na?e tb0f adf mf?f mf1f tb0e ade mf?e mf1e r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 tb0f : time base 0 i nterrupt r equest f lag 0: no request 1: interrupt request bit 6 adf : a/d converter i nterrupt r equest f lag 0: no request 1: interrupt request bit 5 mf2f : multi-function 2 i nterrupt r equest f lag 0: no request 1: interrupt request bit 4 mf1f : multi-function 1 i nterrupt r equest f lag 0: no request 1: interrupt request bit 3 tb0e : time base 0 i nterrupt c ontrol 0: disable 1: enable bit 2 ade : a/d converter i nterrupt c ontrol 0: disable 1: enable bit 1 mf2e : multi-function 2 i nterrupt c ontrol 0: disable 1: enable bit 0 mf1e : multi-function 1 i nterrupt c ontrol 0: disable 1: enable ? na?e urf simf int1f tb1f ure sime int1e tb1e r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 urf : uart i nterrupt r equest f lag 0: no request 1: interrupt request bit 6 simf : sim i nterrupt r equest f lag 0: no request 1: interrupt request bit 5 int1f : int1 pin interrupt request fag 0: no request 1: interrupt request
rev. 1.00 148 de?e??e? 01? ?01? rev. 1.00 149 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom bit 4 tb1f : time base 1 i nterrupt r equest f lag 0: no request 1: interrupt request bit 3 ure : uart i nterrupt control 0: disable 1: enable bit 2 sime : sim i nterrupt control 0: disable 1: enable bit 1 int1e : int1 pin interrupt control 0: disable 1: enable bit 0 tb1e : time base 1 i nterrupt c ontrol 0: disable 1: enable ? na?e stmaf stmpf stmae stmpe r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~6 unimplemented, read as "0" bit 5 stmaf : stm comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 stmpf : stm comparator p match interrupt request fag 0: no request 1: interrupt request bit 3~2 unimplemented, read as "0" bit 1 stmae : stm comparator a match interrupt control 0: disable 1: enable bit 0 stmpe : stm comparator p match interrupt control 0: disable 1: enable ? na?e ctmaf ctmpf ptmaf ptmpf ctmae ctmpe ptmae ptmpe r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 ctmaf : ctm comparator a match interrupt request fag 0: no request 1: interrupt request bit 6 ctmpf : ctm comparator p match interrupt request fag 0: no request 1: interrupt request bit 5 ptmaf : ptm comparator a match interrupt request fag 0: no request 1: interrupt request
rev. 1.00 150 de?e??e? 01? ?01? rev. 1.00 151 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom bit 4 ptmpf : ptm comparator p match interrupt request fag 0: no request 1: interrupt request bit 3 ctmae : ctm comparator a match interrupt control 0: disable 1: enable bit 2 ctmpe : ctm comparator p match interrupt control 0: disable 1: enable bit 1 ptmae : ptm comparator a match interrupt control 0: disable 1: enable bit 0 ptmpe : ptm comparator p match interrupt control 0: disable 1: enable ? mfi2 register bit 7 6 5 4 3 2 1 0 na?e def lvf dee lve r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~6 unimplemented, read as "0" bit 5 def : data eeprom interrupt request fag 0: no request 1: interrupt request bit 4 lvf : lvd interrupt request fag 0: no request 1: interrupt request bit 3~2 unimplemented, read as "0" bit 1 dee : data eeprom nterrupt c ontrol 0: disable 1: enable bit 0 lve : lvd nterrupt c ontrol 0: disable 1: enable interrupt operation when the conditions for an interrupt event occur, such as a tm comparator p, comparator a match or a/d conversion completion etc., the relevant interrupt request fag will be set. whether the request fag actually generates a program jump to the relevant interrupt vector is determined by the condition of the interrupt enable bit. if the enable bit is set high then the program will jump to its relevant vector, if the enable bit is zero then although the interrupt request f ag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector. the global interrupt enable bit, if cleared to zero, will disable all interrupts. when an interrupt is generated, the program counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. the program counter will then be loaded with a new address which will be the value of the corresponding interrupt vector. the microcontroller will then fetch its next instruction from this interrupt vector. the instruction at this vector will usually be a "jmp" which will jump to another section of program which is known as the interrupt service routine. here is located the code to control the appropriate interrupt. the interrupt service routine must be terminated with a "reti", which retrieves the original program counter address from
rev. 1.00 150 de?e??e? 01? ?01? rev. 1.00 151 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. the various interrupt enable bits, together with their associated request flags, are shown in the accompanying diagrams with their order of priority. some interrupt sources have their own individual vector while others share the same multi-function interrupt vector. once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the global interrupt enable bit, emi bit will be cleared automatically. this will prevent any further interrupt nesting from occurring. however, if other interrupt requests occur during this interval, although the interrupt will not be immediately serviced, the request fag will still be recorded. if an interrupt requires immediate servicing while the program is already in another interrupt service routine, the emi bit should be set after entering the routine, to allow interrupt nesting. if the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. if immediate service is desired, the stack must be prevented from becoming full. in case of simultaneous requests, the accompanying diagram shows the priority that is applied. all of the interrupt request f ags when set will wake-up the device if it is in sleep or idle mode, however to prevent a wake-up from occurring the corresponding fag should be set before the device is in sleep or idle mode. int0 pin int1 pin int0f int1f int0e int1e emi 04h emi 08h emi 0ch emi 10h ti?e base 0 tb0f tb0e ctm p ctmpf ctmpe emi 1ch inte??upt na?e request flags ena?le bits maste? ena?le vector emi auto disa?led in isr p?io?ity high low stm p stmpf stmpe stm a stmaf stmae m. fun?t. 0 mf0f mf0e inte??upts ?ontained within multi-fun?tion inte??upts xxe ena?le bits xxf request flag? auto ?eset in isr legend xxf request flag? no auto ?eset in isr emi ?0h emi ?4h co?pa?ato? cpf cpe m. fun?t. 1 mf1f mf1e ti?e base 1 tb1f tb1e ctm a ctmaf ctmae a/d ?onve?te? adf ade emi 18h emi 14h lvd lvf lve m. fun?t. ? mf?f mf?e eeprom def dee ptm p ptmpf ptmpe ptm a ptmaf ptmae uart urf ure emi ?8h emi ?ch sim simf sime interrupt structure
rev. 1.00 15? de?e??e? 01? ?01? rev. 1.00 153 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom external interrupts the external interrupts are controlled by signal transitions on the pins int0~int1. an external interrupt request will take place when the external interrupt request fags, int0f~int1f, are set, which will occur when a transition, whose type is chosen by the edge select bits, appears on the external interrupt pins. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and respective external interrupt enable bit, int0e~int1e, must frst be set. additionally the correct interrupt edge type must be selected using the integ register to enable the external interrupt function and to choose the trigger edge type. as the external interrupt pins are pin-shared with i/o pins, they can only be configured as external interrupt pins if their external interrupt enable bit in the corresponding interrupt register has been set. the pin must also be setup as an input by setting the corresponding bit in the port control register. when the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector, will take place. when the interrupt is serviced, the external interrupt request fags, int0f~int1f, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. note that any pull-high resistor selections on the external interrupt pins will remain valid even if the pin is used as an external interrupt input. the integ register is used to select the type of active edge that will trigger the external interrupt. a choice of either rising or falling or both edge types can be chosen to trigger an external interrupt. note that the integ register can also be used to disable the external interrupt function. comparator interrupt the comparator interrupt is controlled by the internal comparator. a comparator interrupt request will take place when the comparator interrupt request fag, cpf, is set, a situation that will occur when the comparator output bit changes state. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and comparator interrupt enable bit, cpe, must frst be set. when the interrupt is enabled, the stack is not full and the comparator inputs generate a comparator output transition, a subroutine call to the comparator interrupt vector, will take place. when the interrupt is serviced, the comparator interrupt request fag will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. multi-function interrupts within the device there are three multi-function interrupts. unlike the other independent interrupts, these interrupts have no independent source, but rather are formed from other existing interrupt sources, namely the tm interrupts, lvd interrupt and eeprom write operation interrupt. a multi-function interrupt request will take place when any of the multi-function interrupt request flags mfnf are set. the multi-function interrupt flags will be set when any of their included functions generate an interrupt request fag. when the multi-function interrupt is enabled and the stack is not full, and either one of the interrupts contained within each of multi-function interrupt occurs, a subroutine call to one of the multi-function interrupt vectors will take place. when the interrupt is serviced, the related multi-function request fag will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. however, it must be noted that, although the multi-function interrupt request flags will be automatically reset when the interrupt is serviced, the request flags from the original source of the multi-function interrupts will not be automatically reset and must be manually reset by the application program.
rev. 1.00 15? de?e??e? 01? ?01? rev. 1.00 153 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom a/d converter interrupt the device contains an a/d converter which has its own independent interrupt. the a/d converter interrupt is controlled by the termination of an a/d conversion process. an a/d converter interrupt request will take place when the a/d converter interrupt request fag, adf, is set, which occurs when the a/d conversion process fnishes. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and a/d converter interrupt enable bit, ade, must frst be set. when the interrupt is enabled, the stack is not full and the a/d conversion process has ended, a subroutine call to the a/d converter interrupt vector, will take place. when the interrupt is serviced, the a/d converter interrupt fag, adf, will be automatically cleared. the emi bit will also be automatically cleared to disable other interrupts. time base interrupts the function of the time base interrupts is to provide regular time signal in the form of an internal interrupt. they are controlled by the overfow signals from their respective timer functions. when these happens their respective interrupt request flags, tb0f or tb1f will be set. to allow the program to branch to their respective interrupt vector addresses, the global interrupt enable bit, emi and time base enable bits, tb0e or tb1e, must frst be set. when the interrupt is enabled, the stack is not full and the time base overfows, a subroutine call to their respective vector locations will take place. when the interrupt is serviced, the respective interrupt request fag, tb0f or tb1f, will be automatically reset and the emi bit will be cleared to disable other interrupts. the purpose of the time base interrupt is to provide an interrupt signal at fxed time periods. their clock sources originate from the internal clock source f tb . this f tb input clock passes through a divider, the division ratio of which is selected by programming the appropriate bits in the tbc register to obtain longer interrupt periods whose value ranges. the clock source that generates f tb , which in turn controls the time base interrupt period, can originate from several different sources, as shown in the system operating mode section. f sys /4 m u x f tb ti?e base 0 inte??upt ti?e base 1 inte??upt tb0? ~ tb00 tb11 ~ tb10 ? 8 ~ ? 15 ? 1? ~ ? 15 lirc f tbc tbck bit m u x lxt configu?ation option time base interrupts ? tbc register bit 7 6 5 4 3 2 1 0 na?e tbon tbck tb11 tb10 lxtlp tb0? tb01 tb00 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 1 1 0 1 1 1 bit 7 tbon : time base 0 and time base 1 enable control 0: disable 1: enable bit 6 tbck : select f tb clock 0: f tbc 1: f /4
rev. 1.00 154 de?e??e? 01? ?01? rev. 1.00 155 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom bit 5~4 tb11~tb10 : time base 1 time-out period selection 00: 2 12 /f tb 01: 2 13 /f tb 10: 2 14 /f tb 11: 2 15 / f tb bit 3 lxtlp : lxt low power control 0: disable (lxt quick start-up) 1: enable (lxt slow start-up) bit 2~0 tb02~tb00 : time base 0 time-out period selection 000: 2 8 /f tb 001: 2 9 /f tb 010: 2 10 /f tb 011: 2 11 /f tb 100: 2 12 /f tb 101: 2 13 /f tb 110: 2 14 /f tb 111: 2 15 /f tb an sim interrupt request will take place when the sim interrupt request fag, simf, is set, which occurs when a byte of data has been received or transmitted by the sim interface, an i 2 c slave address match or i 2 c bus time-out occurrence. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and the serial interface interrupt enable bit, sime, must frst be set. when the interrupt is enabled, the stack is not full and any of the above described situations occurs, will take place. when the serial interface module interrupt is serviced, the interrupt request fag, simf, will be automatically reset and the emi bit will be cleared to disable other interrupts. the uart transfer interrupt is controlled by several uart transfer conditions. when one of these conditions occurs, an interrupt pulse will be generated to get the attention of the microcontroller. these conditions are a transmitter data register empty, transmitter idle, receiver data available, receiver overrun, address detect and an rx pin wake-up. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and uart interrupt enable bit, ure, must frst be set. when the interrupt is enabled, the stack is not full and any of the conditions described above occurs, a subroutine call to the uart interrupt vector, will take place. when the interrupt is serviced, the uart interrupt fag, urf, will be automatically cleared. the emi bit will also be automatically cleared to disable other interrupts. the eeprom write interrupt is contained within the multi-function interrupt. an eeprom write interrupt request will take place when the eeprom write interrupt request fag, def, is set, which occurs when an eeprom write cycle ends. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, eeprom write interrupt enable bit, dee, and associated multi-function interrupt enable bit must first be set. when the interrupt is enabled, the stack is not full and an eeprom write cycle ends, a subroutine call to the respective multi-function interrupt vector will take place. when the eeprom write interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts. however, only the multi-function interrupt request flag will be automatically cleared. as the def flag will not be automatically cleared, it has to be cleared by the application program.
rev. 1.00 154 de?e??e? 01? ?01? rev. 1.00 155 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom lvd interrupt the low voltage detector interrupt is contained within the multi-function interrupt. a lvd interrupt request will take place when the lvd interrupt request flag, lvf, is set, which occurs when the low voltage detector function detects a low power supply voltage. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, low voltage interrupt enable bit, lve, and associated multi-function interrupt enable bit, must frst be set. when the interrupt is enabled, the stack is not full and a low voltage condition occurs, a subroutine call to the multi-function interrupt vector, will take place. when the low voltage interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the multi-function interrupt request fag will be also automatically cleared. as the lvf fag will not be automatically cleared, it has to be cleared by the application program. tm interrupts the compact, standard and periodic tms have two interrupts, one comes from the comparator a match situation and the other comes from the comparator p match situation. all of the tm interrupts are contained within the multi-function interrupts. for all of the tm types there are two interrupt request fags and two enable control bits. a tm interrupt request will take place when any of the tm request fags are set, a situation which occurs when a tm comparator p or a match situation happens. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, respective tm interrupt enable bit, and relevant multi-function interrupt enable bit, mfne, must frst be set. when the interrupt is enabled, the stack is not full and a tm comparator match situation occurs, a subroutine call to the relevant multi-function interrupt vector locations, will take place. when the tm interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts. however, only the related mfnf fag will be automatically cleared. as the tm interrupt request fags will not be automatically cleared, they have to be cleared by the application program. interrupt wake-up function each of the interrupt functions has the capability of waking up the microcontroller when in the sleep or idle mode. a wake-up is generated when an interrupt request fag changes from low to high and is independent of whether the interrupt is enabled or not. therefore, even though the device is in the sleep or idle mode and its system oscillator stopped, situations such as external edge transitions on the external interrupt pins, a low power supply voltage or comparator input change may cause their respective interrupt fag to be set high and consequently generate an interrupt. care must therefore be taken if spurious wake-up situations are to be avoided. if an interrupt wake-up function is to be disabled then the corresponding interrupt request fag should be set high before the device enters the sleep or idle mode. the interrupt enable bits have no effect on the interrupt wake-up function.
rev. 1.00 156 de?e??e? 01? ?01? rev. 1.00 15? de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom programming considerations by disabling the relevant interrupt enable bits, a requested interrupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request fag is cleared by the application program. where a certain interrupt is contained within a multi-function interrupt, then when the interrupt service routine is executed, as only the multi-function interrupt request flags, mfnf, will be automatically cleared, the individual request flag for the function needs to be cleared by the application program. it is recommended that programs do not use the "call" instruction within the interrupt service subroutine. interrupts often occur in an unpredictable manner or need to be serviced immediately. if only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged once a call subroutine is executed in the interrupt subroutine. every interrupt has the capability of waking up the microcontroller when it is in sleep or idle mode, the wake up being generated when the interrupt request fag changes from low to high. if it is required to prevent a certain interrupt from waking up the microcontroller then its respective request fag should be frst set high before enter sleep or idle mode. as only the program counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator, status register or other registers are altered by the interrupt service program, their contents should be saved to the memory at the beginning of the interrupt service routine. to return from an interrupt subroutine, either a ret or reti instruction may be executed. the reti instruction in addition to executing a return to the main program also automatically sets the emi bit high to allow further interrupts. the ret instruction however only executes a return to the main program leaving the emi bit in its present zero state and therefore disabling the execution of further interrupts.
rev. 1.00 156 de?e??e? 01? ?01? rev. 1.00 15? de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom low voltage detector C lvd this device has a low voltage detector function, also known as lvd. this enabled the device to monitor the power supply voltage, v dd , and provide a warning signal should it fall below a certain level. this function may be especially useful in battery applications where the supply voltage will gradually reduce as the battery ages, as it allows an early warning battery low signal to be generated. the low voltage detector also has the capability of generating an interrupt signal. lvd register the low voltage detector function is controlled using a single register with the name lvdc. three bits in this register, vlvd2~vlvd0, are used to select one of eight fxed voltages below which a low voltage condition will be determined. a low voltage condition is indicated when the lvdo bit is set. if the lvdo bit is low, this indicates that the v dd voltage is above the preset low voltage value. the lvden bit is used to control the overall on/off function of the low voltage detector. setting the bit high will enable the low voltage detector. clearing the bit to zero will switch off the internal low voltage detector circuits. as the low voltage detector will consume a certain amount of power, it may be desirable to switch off the circuit when not in use, an important consideration in power sensitive battery powered applications. ? lvdc register bit 7 6 5 4 3 2 1 0 na?e lvdo lvden vbgen vlvd ? vlvd1 vlvd0 r/w r r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 unimplemented, read as "0" bit 5 : lvd output flag 0: no low voltage detect 1: low voltage detect bit 4 : low voltage detector control 0: disable 1: enable bit 3 : bandgap buffer control 0: disable 1: enable note that the bandgap circuit is enabled when the lvd or the lvr function is enabled or when the vbgen bit is set high. bit 2~0 : select lvd voltage 000: 2.0v 001: 2.2v 010: 2.4v 011: 2.7v 100: 3.0v 101: 3.3v 110: 3.6v 111: 4.0v
rev. 1.00 158 de?e??e? 01? ?01? rev. 1.00 159 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom lvd operation the low voltage detector function operates by comparing the power supply voltage, v dd , with a pre-specifed voltage level stored in the lvdc register. this has a range of between 2.0v and 4.0v. when the power supply voltage, v dd , falls below this pre-determined value, the lvdo bit will be set high indicating a low power supply voltage condition. when the device is in the sleep and idle mode, the low voltage detector will remain active if the lvden bit is high. after enabling the low voltage detector, a time delay t lvds should be allowed for the circuitry to stabilise before reading the lvdo bit. note also that as the v dd voltage may rise and fall rather slowly, at the voltage nears that of v lvd , there may be multiple bit lvdo transitions. vdd lvden lvdo v lvd t lvds lvd operation the low voltage detector also has its own interrupt which is contained within one of the multi- function interrupts, providing an alternative means of low voltage detection, in addition to polling the lvdo bit. the interrupt will only be generated after a delay of t lvd after the lvdo bit has been set high by a low voltage condition. in this case, the lvf interrupt request fag will be set, causing an interrupt to be generated if v dd falls below the preset lvd voltage. this will cause the device to wake-up from the sleep or idle mode, however if the low voltage detector wake up function is not required then the lvf fag should be frst set high before the device enters the sleep or idle mode. when lvd function is enabled, it is recommenced to clear lvd fag frst, and then enables interrupt function to avoid mistake action.
rev. 1.00 158 de?e??e? 01? ?01? rev. 1.00 159 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom confguration options confguration options refer to certain options within the mcu that are programmed into the device during the programming process. during the development process, these options are selected using the ht-ide software development tools. as these options are programmed into the device using the hardware programming tools, once they are selected they cannot be changed later using the application program. all options must be defned for proper system function, the details of which are shown in the table. no. options 1 high speed syste? os?illato? sele?tion C f h : hxt hirc ? low speed syste? os?illato? sele?tion C f sub : lxt lirc 3 hirc f?equen?y sele?tion 8mhz 1?mhz 16mhz application circuits pa0~pa? an0~an? vdd vss v dd 0.1 f pb0~pb6 pc0~pc? pc0/osc1 pc1/osc? osc ci??uit pb0/xt1 pb1/xt? osc ci??uit see os?illato? se?tion see os?illato? se?tion
rev. 1.00 160 de?e??e? 01? ?01? rev. 1.00 161 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. in the case of holtek microcontroller, a comprehensive and fexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. for easier understanding of the various instruction codes, they have been subdivided into several functional groupings. instruction timing most instructions are implemented within one instruction cycle. the exceptions to this are branch, call, or table read instructions where two instruction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator, most instructions would be implemented within 0.5s and branch or call instructions would be implemented within 1s. although instructions which require one more cycle to implement are generally limited to the jmp, call, ret, reti and table read instructions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to implement. as instructions which change the contents of the pcl will imply a direct jump to that new address, one more cycle will be required. examples of such instructions would be "clr pcl" or "mov pcl, a". for the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the transfer of data within the microcontroller program is one of the most frequently used operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specifc immediate data directly into the accumulator. one of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. within the holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specifed.
rev. 1.00 160 de?e??e? 01? ?01? rev. 1.00 161 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom logical and rotate operation the standard logical operations such as and, or, xor and cpl all have their own instruction within the holtek microcontroller instruction set. as with the case of most instructions involving data manipulation, data must pass through the accumulator which may involve additional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. different rotate instructions exist depending on program requirements. rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the carry bit from where it can be examined and the necessary serial bit set high or low. another application which rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specifed locations using the jmp instruction or to a subroutine using the call instruction. they differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. this is done by placing a return instruction "ret" in the subroutine which will cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping off point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is frst made regarding the condition of a certain data memory or individual bits. depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. these instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits. bit operations the ability to provide single bit operations on data memory is an extremely fexible feature of all holtek microcontrollers. this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the "set [m].i" or "clr [m]. i" instructions respectively. the feature removes the need for programmers to frst read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write process is taken care of automatically when these bit operation instructions are used. table read operations data storage is normally implemented by using registers. however, when working with large amounts of fxed data, the volume involved often makes it inconvenient to store the fxed data in the data memory. to overcome this problem, holtek microcontrollers allow an area of program memory to be set as a table where data can be directly stored. a set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the "halt" instruction for power-down operations and instructions to control the operation of the watchdog timer for reliable program operations under extreme electric or electromagnetic environments. for their relevant operations, refer to the functional related sections.
rev. 1.00 16? de?e??e? 01? ?01? rev. 1.00 163 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom instruction set summary the following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. table conventions x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a?[?] add data me?o? y to acc 1 z? c? ac? ov addm a?[?] add acc to data me ?o?y 1 note z? c? ac? ov add a?x add i?? ediate data to acc 1 z? c? ac? ov adc a?[?] add data me?o? y to acc with ca??y 1 z? c? ac? ov adcm a?[?] add acc to data ?e?o?y with ca??y 1 note z? c? ac? ov sub a?x su?t?a?t i??ediate data f?o? the acc 1 z? c? ac? ov sub a?[?] su?t?a?t data me?o?y f?o? acc 1 z? c? ac? ov subm a?[?] su?t?a?t data me?o?y f?o? acc with ?esult in data me?o?y 1 note z? c? ac? ov sbc a?[?] su?t?a?t data me?o?y f?o? acc with ca??y 1 z? c? ac? ov sbcm a?[?] su?t?a?t data me?o?y f?o? acc with ca??y ? ?esult in data me?o?y 1 note z? c? ac? ov daa [ ?] de?i? al adjust acc fo? addition with ?esult in data me?o?y 1 note c logic operation and a?[?] logi? al and data me?o? y to acc 1 z or a?[?] logi?al or data me?o? y to acc 1 z xor a?[?] logi?al xor data me?o? y to acc 1 z andm a?[?] logi? al and acc to data me?o?y 1 note z orm a?[?] logi? al or acc to data me?o?y 1 note z xorm a?[?] logi? al xor acc to data me?o?y 1 note z and a?x logi? al and i?? ediate data to acc 1 z or a?x logi?al or i?? ediate data to acc 1 z xor a?x logi?al xor i?? ediate data to acc 1 z cpl [ ?] co?ple?ent data me?o?y 1 note z cpla [ ?] co?ple?ent data me?o?y with ? esult in acc 1 z increment & decrement inca [ ?] in??e?ent data me?o?y with ? esult in acc 1 z inc [?] in??e?ent data me?o?y 1 note z deca [ ?] de??e?ent data me?o?y with ? esult in acc 1 z dec [?] de??e?ent data me?o?y 1 note z rotate rra [ ?] rotate data me?o?y ?ight with ? esult in acc 1 none rr [?] rotate data me?o?y ?ight 1 note none rrca [ ?] rotate data me?o?y ?ight th?ough ca??y with ? esult in acc 1 c rrc [?] rotate data me?o?y ?ight th?ough ca??y 1 note c rla [ ?] rotate data me?o?y left with ? esult in acc 1 none rl [ ?] rotate data me?o?y left 1 note none rlca [ ?] rotate data me?o?y left th?ough ca??y with ? esult in acc 1 c rlc [?] rotate data me?o?y left th?ough ca??y 1 note c
rev. 1.00 16? de?e??e? 01? ?01? rev. 1.00 163 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom mnemonic description cycles flag affected data move mov a ?[?] move data me?o? y to acc 1 none mov [?]?a move acc to data me ?o?y 1 note none mov a ?x move i?? ediate data to acc 1 none bit operation clr [?].i clea? ?it of data me?o?y 1 note none set [ ?].i set ?it of data me?o?y 1 note none branch operation jmp add ? ju?p un?onditionally ? none sz [?] skip if data me?o?y is ze?o 1 note none sza [ ?] skip if data me?o?y is ze?o with data ?ove? ent to acc 1 note none sz [?].i skip if ?it i of data me?o?y is ze?o 1 note none snz [?].i skip if ?it i of data me?o?y is not ze?o 1 note none siz [?] skip if in??e?ent data me?o?y is ze?o 1 note none sdz [?] skip if de??e?ent data me?o?y is ze?o 1 note none siza [ ?] skip if in??e?ent data me?o?y is ze?o with ? esult in acc 1 note none sdza [ ?] skip if de??e?ent data me?o?y is ze?o with ? esult in acc 1 note none call add ? su??outine ?all ? none ret retu?n f?o? su??outine ? none ret a ?x retu?n f?o? su??outine and load i?? ediate data to acc ? none reti retu?n f?o? inte??upt ? none table read operation tabrd [ ?] read table (specifc page) to tblh and data memory ? note none tabrdc [ ?] read ta?le (?u?? ent page) to tblh and data me?o?y ? note none tabrdl [ ?] read ta? le (last page) to tblh and data me?o?y ? note none miscellaneous nop no ope?ation 1 none clr [?] clea? data me?o?y 1 note none set [ ?] set data me?o?y 1 note none clr wdt clea? wat? hdog ti?e? 1 to ? pdf clr wdt1 p?e-?lea? wat? hdog ti?e? 1 to ? pdf clr wdt? p?e-?lea? wat? hdog ti?e? 1 to ? pdf swap [ ?] swap ni??les of data me?o?y 1 note none swapa [ ?] swap ni??les of data me?o?y with ? esult in acc 1 none halt ente? powe? down ?ode 1 to ? pdf notes: 1. for skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for the "clr wdt1" and "clr wdt2" instructions the to and pdf fags may be affected by the execution status. the to and pdf flags are cleared after both "clr wdt1" and "clr wdt2" instructions are consecutively executed. otherwise the to and pdf fags remain unchanged.
rev. 1.00 164 de?e??e? 01? ?01? rev. 1.00 165 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom instruction defnition adc a,[m] add data memory to acc with carry description the contents of the specifed data memory, accumulator and the carry fag are added. the result is stored in the accumulator. operation acc acc + [m] + c affected fag(s) ov, z, ac, c adcm a,[m] add acc to data memory with carry description the contents of the specifed data memory, accumulator and the carry fag are added. the result is stored in the specifed data memory. operation [m] acc + [m] + c affected fag(s) ov, z, ac, c add a,[m] add data memory to acc description the contents of the specifed data memory and the accumulator are added. the result is stored in the accumulator. operation acc acc + [m] affected fag(s) ov, z, ac, c add a,x add immediate data to acc description the contents of the accumulator and the specifed immediate data are added. the result is stored in the accumulator. operation acc acc + x affected fag(s) ov, z, ac, c addm a,[m] add acc to data memory description the contents of the specifed data memory and the accumulator are added. the result is stored in the specifed data memory. operation [m] acc + [m] affected fag(s) ov, z, ac, c and a,[m] logical and data memory to acc description data in the accumulator and the specifed data memory perform a bitwise logical and operation. the result is stored in the accumulator. operation acc acc and [m] affected fag(s) z and a,x logical and immediate data to acc description data in the accumulator and the specifed immediate data perform a bit wise logical and operation. the result is stored in the accumulator. operation acc acc and x affected fag(s) z andm a,[m] logical and acc to data memory description data in the specifed data memory and the accumulator perform a bitwise logical and operation. the result is stored in the data memory. operation [m] acc and [m] affected fag(s) z
rev. 1.00 164 de?e??e? 01? ?01? rev. 1.00 165 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom call addr subroutine call description unconditionally calls a subroutine at the specifed address. the program counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. the specifed address is then loaded and the program continues execution from this new address. as this instruction requires an additional operation, it is a two cycle instruction. operation stack program counter + 1 program counter addr affected fag(s) none clr [m] clear data memory description each bit of the specifed data memory is cleared to 0. operation [m] 00h affected fag(s) none clr [m].i clear bit of data memory description bit i of the specifed data memory is cleared to 0. operation [m].i 0 affected fag(s) none clr wdt clear watchdog timer description the to, pdf fags and the wdt are all cleared. operation wdt cleared to 0 pdf 0 affected fag(s) to, pdf clr wdt1 pre-clear watchdog timer description the to, pdf fags and the wdt are all cleared. note that this instruction works in conjunction with clr wdt2 and must be executed alternately with clr wdt2 to have effect. repetitively executing this instruction without alternately executing clr wdt2 will have no effect. operation wdt cleared to 0 pdf 0 affected fag(s) to, pdf clr wdt2 pre-clear watchdog timer description the to, pdf fags and the wdt are all cleared. note that this instruction works in conjunction with clr wdt1 and must be executed alternately with clr wdt1 to have effect. repetitively executing this instruction without alternately executing clr wdt1 will have no effect. operation wdt cleared to 0 pdf 0 affected fag(s) to, pdf cpl [m] complement data memory description each bit of the specifed data memory is logically complemented (1s complement). bits which previously contained a 1 are changed to 0 and vice versa. operation [m] [m] affected fag(s) z
rev. 1.00 166 de?e??e? 01? ?01? rev. 1.00 16? de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom cpla [m] complement data memory with result in acc description each bit of the specifed data memory is logically complemented (1s complement). bits which previously contained a 1 are changed to 0 and vice versa. the complemented result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc [m] affected fag(s) z daa [m] decimal-adjust acc for addition with result in data memory description convert the contents of the accumulator value to a bcd (binary coded decimal) value resulting from the previous addition of two bcd variables. if the low nibble is greater than 9 or if ac fag is set, then a value of 6 will be added to the low nibble. otherwise the low nibble remains unchanged. if the high nibble is greater than 9 or if the c fag is set, then a value of 6 will be added to the high nibble. essentially, the decimal conversion is performed by adding 00h, 06h, 60h or 66h depending on the accumulator and fag conditions. only the c fag may be affected by this instruction which indicates that if the original bcd sum is greater than 100, it allows multiple precision decimal addition. operation [m] acc + 00h or [m] acc + 06h or [m] acc + 60h or [m] acc + 66h affected fag(s) c dec [m] decrement data memory description data in the specifed data memory is decremented by 1. operation [m] [m] ? 1 affected fag(s) z deca [m] decrement data memory with result in acc description data in the specifed data memory is decremented by 1. the result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc [m] ? 1 affected fag(s) z halt enter power down mode description this instruction stops the program execution and turns off the system clock. the contents of the data memory and registers are retained. the wdt and prescaler are cleared. the power down fag pdf is set and the wdt time-out fag to is cleared. operation to 0 pdf 1 affected fag(s) to, pdf inc [m] increment data memory description data in the specifed data memory is incremented by 1. operation [m] [m] + 1 affected fag(s) z inca [m] increment data memory with result in acc description data in the specifed data memory is incremented by 1. the result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc [m] + 1 affected fag(s) z
rev. 1.00 166 de?e??e? 01? ?01? rev. 1.00 16? de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom jmp addr jump unconditionally description the contents of the program counter are replaced with the specifed address. program execution then continues from this new address. as this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. operation program counter addr affected fag(s) none mov a,[m] move data memory to acc description the contents of the specifed data memory are copied to the accumulator. operation acc [m] affected fag(s) none mov a,x move immediate data to acc description the immediate data specifed is loaded into the accumulator. operation acc x affected fag(s) none mov [m],a move acc to data memory description the contents of the accumulator are copied to the specifed data memory. operation [m] acc affected fag(s) none nop no operation description no operation is performed. execution continues with the next instruction. operation no operation affected fag(s) none or a,[m] logical or data memory to acc description data in the accumulator and the specifed data memory perform a bitwise logical or operation. the result is stored in the accumulator. operation acc acc or [m] affected fag(s) z or a,x logical or immediate data to acc description data in the accumulator and the specifed immediate data perform a bitwise logical or operation. the result is stored in the accumulator. operation acc acc or x affected fag(s) z orm a,[m] logical or acc to data memory description data in the specifed data memory and the accumulator perform a bitwise logical or operation. the result is stored in the data memory. operation [m] acc or [m] affected fag(s) z ret return from subroutine description the program counter is restored from the stack. program execution continues at the restored address. operation program counter stack affected fag(s) none
rev. 1.00 168 de?e??e? 01? ?01? rev. 1.00 169 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom ret a,x return from subroutine and load immediate data to acc description the program counter is restored from the stack and the accumulator loaded with the specifed immediate data. program execution continues at the restored address. operation program counter stack acc x affected fag(s) none reti return from interrupt description the program counter is restored from the stack and the interrupts are re-enabled by setting the emi bit. emi is the master interrupt global enable bit. if an interrupt was pending when the reti instruction is executed, the pending interrupt routine will be processed before returning to the main program. operation program counter stack emi 1 affected fag(s) none rl [m] rotate data memory left description the contents of the specifed data memory are rotated left by 1 bit with bit 7 rotated into bit 0. operation [m].(i+1) [m].i; (i=0~6) [m].0 [m].7 affected fag(s) none rla [m] rotate data memory left with result in acc description the contents of the specifed data memory are rotated left by 1 bit with bit 7 rotated into bit 0. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; (i=0~6) acc.0 [m].7 affected fag(s) none rlc [m] rotate data memory left through carry description the contents of the specifed data memory and the carry fag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry fag is rotated into bit 0. operation [m].(i+1) [m].i; (i=0~6) [m].0 c c [m].7 affected fag(s) c rlca [m] rotate data memory left through carry with result in acc description data in the specifed data memory and the carry fag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry fag is rotated into the bit 0. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; (i=0~6) acc.0 c c [m].7 affected fag(s) c rr [m] rotate data memory right description the contents of the specifed data memory are rotated right by 1 bit with bit 0 rotated into bit 7. operation [m].i [m].(i+1); (i=0~6) [m].7 [m].0 affected fag(s) none
rev. 1.00 168 de?e??e? 01? ?01? rev. 1.00 169 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom rra [m] rotate data memory right with result in acc description data in the specifed data memory is rotated right by 1 bit with bit 0 rotated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i=0~6) acc.7 [m].0 affected fag(s) none rrc [m] rotate data memory right through carry description the contents of the specifed data memory and the carry fag are rotated right by 1 bit. bit 0 replaces the carry bit and the original carry fag is rotated into bit 7. operation [m].i [m].(i+1); (i=0~6) [m].7 c c [m].0 affected fag(s) c rrca [m] rotate data memory right through carry with result in acc description data in the specifed data memory and the carry fag are rotated right by 1 bit. bit 0 replaces the carry bit and the original carry fag is rotated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i=0~6) acc.7 c c [m].0 affected fag(s) c sbc a,[m] subtract data memory from acc with carry description the contents of the specifed data memory and the complement of the carry fag are subtracted from the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. operation acc acc ? [m] ? c affected fag(s) ov, z, ac, c sbcm a,[m] subtract data memory from acc with carry and result in data memory description the contents of the specifed data memory and the complement of the carry fag are subtracted from the accumulator. the result is stored in the data memory. note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. operation [m] acc ? [m] ? c affected fag(s) ov, z, ac, c sdz [m] skip if decrement data memory is 0 description the contents of the specifed data memory are frst decremented by 1. if the result is 0 the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m] ? 1 skip if [m]=0 affected fag(s) none
rev. 1.00 1?0 de?e??e? 01? ?01? rev. 1.00 1?1 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom sdza [m] skip if decrement data memory is zero with result in acc description the contents of the specifed data memory are frst decremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specifed data memory contents remain unchanged. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation acc [m] ? 1 skip if acc=0 affected fag(s) none set [m] set data memory description each bit of the specifed data memory is set to 1. operation [m] ffh affected fag(s) none set [m].i set bit of data memory description bit i of the specifed data memory is set to 1. operation [m].i 1 affected fag(s) none siz [m] skip if increment data memory is 0 description the contents of the specifed data memory are frst incremented by 1. if the result is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m] + 1 skip if [m]=0 affected fag(s) none siza [m] skip if increment data memory is zero with result in acc description the contents of the specifed data memory are frst incremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specifed data memory contents remain unchanged. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m] + 1 skip if acc=0 affected fag(s) none snz [m].i skip if bit i of data memory is not 0 description if bit i of the specifed data memory is not 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is 0 the program proceeds with the following instruction. operation skip if [m].i 0 affected fag(s) none sub a,[m] subtract data memory from acc description the specifed data memory is subtracted from the contents of the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. operation acc acc ? [m] affected fag(s) ov, z, ac, c
rev. 1.00 1?0 de?e??e? 01? ?01? rev. 1.00 1?1 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom subm a,[m] subtract data memory from acc with result in data memory description the specifed data memory is subtracted from the contents of the accumulator. the result is stored in the data memory. note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. operation [m] acc ? [m] affected fag(s) ov, z, ac, c sub a,x subtract immediate data from acc description the immediate data specifed by the code is subtracted from the contents of the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. operation acc acc ? x affected fag(s) ov, z, ac, c swap [m] swap nibbles of data memory description the low-order and high-order nibbles of the specifed data memory are interchanged. operation [m].3~[m].0 ? [m].7~[m].4 affected fag(s) none swapa [m] swap nibbles of data memory with result in acc description the low-order and high-order nibbles of the specifed data memory are interchanged. the result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc.3~acc.0 [m].7~[m].4 acc.7~acc.4 [m].3~[m].0 affected fag(s) none sz [m] skip if data memory is 0 description if the contents of the specifed data memory is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation skip if [m]=0 affected fag(s) none sza [m] skip if data memory is 0 with data movement to acc description the contents of the specifed data memory are copied to the accumulator. if the value is zero, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m] skip if [m]=0 affected fag(s) none sz [m].i skip if bit i of data memory is 0 description if bit i of the specifed data memory is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation skip if [m].i=0 affected fag(s) none
rev. 1.00 1?? de?e??e? 01? ?01? rev. 1.00 1?3 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom tabrd [m] read table (specifc page) to tblh and data memory description the low byte of the program code (specifc page) addressed by the table pointer pair (tbhp and tblp) is moved to the specifed data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected fag(s) none tabrdc [m] read table (current page) to tblh and data memory description the low byte of the program code (current page) addressed by the table pointer (tblp) is moved to the specifed data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected fag(s) none tabrdl [m] read table (last page) to tblh and data memory description the low byte of the program code (last page) addressed by the table pointer (tblp) is moved to the specifed data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected fag(s) none xor a,[m] logical xor data memory to acc description data in the accumulator and the specifed data memory perform a bitwise logical xor operation. the result is stored in the accumulator. operation acc acc xor [m] affected fag(s) z xorm a,[m] logical xor acc to data memory description data in the specifed data memory and the accumulator perform a bitwise logical xor operation. the result is stored in the data memory. operation [m] acc xor [m] affected fag(s) z xor a,x logical xor immediate data to acc description data in the accumulator and the specifed immediate data perform a bitwise logical xor operation. the result is stored in the accumulator. operation acc acc xor x affected fag(s) z
rev. 1.00 1?? de?e??e? 01? ?01? rev. 1.00 1?3 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom package information note that the package information provided here is for consultation purposes only. as this information may be updated at regular intervals users are reminded to consult the holtek website for the latest version of the package/carton information . additional supplementary information with regard to packaging is listed below. click on the relevant section to be transferred to the relevant website page. ? further package information (include outline dimensions, product tape and reel specifcations) ? packing meterials information ? carton information
rev. 1.00 1?4 de?e??e? 01? ?01? rev. 1.00 1?5 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom 20-pin nsop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0.??8 0.?36 0.?44 b 0.146 0.154 0.161 c 0.009 0.01? c 0.38? 0.390 0.398 d 0.069 e 0.03? bsc f 0.00? 0.009 g 0.0?0 0.031 h 0.008 0.010 0 8 symbol dimensions in mm min. nom. max. a 5.80 6.00 6.?0 b 3.?0 3.90 4.10 c 0.?3 0.30 c 9.?0 9.90 10.10 d 1.?5 e 0.80 bsc f 0.05 0.?3 g 0.50 0.80 h 0.?1 0.?5 0 8
rev. 1.00 1?4 de?e??e? 01? ?01? rev. 1.00 1?5 de?e??e? 01? ?01? HT66F019 a/d flash mcu with eeprom HT66F019 a/d flash mcu with eeprom copy?ight ? ?01? ? y holtek semiconductor inc. the info?? ation appea?ing in this data sheet is ?elieved to ?e a??u? ate at the ti? e of pu ?li? ation. howeve ?? holtek assu? es no ?esponsi? ility a? ising f?o? the use of the specifcations described. the applications mentioned herein are used solely fo? the pu?pose of illust?ation and holtek ?akes no wa??anty o? ?ep?esentation that su? h appli? ations will ? e suita? le without fu?the? ?odifi?ation? no? ?e?o?? ends the use of its p?odu?ts fo? appli?ation that ?ay p?esent a ?isk to hu?an life due to ? alfun?tion o? othe? wise. holtek's p?odu? ts a? e not autho?ized fo? use as ?? iti? al ?o?ponents in life suppo?t devi?es o? syste?s. holtek ?ese?ves the ?ight to alte? its products without prior notifcation. for the most up-to-date information, please visit ou? we? site at http://www.holtek.?o?/en/.

▲Up To Search▲

Price & Availability of HT66F019

	To Download HT66F019 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .